--- In 68HC12@68HC..., "Sam Saprunoff" <sams2@t...> wrote: ... > Anyway, now that I know of this issue it no longer affects my design. > However, I wanted to give others a "heads up" in case they run into this > issue. > > Cheers, > > Sam According to Freescale, you will be forced to upgrade your product to the maskset of MC9S12DT128. Anybody know if that maskset does not have the limitation?

Good day Zoltan, Indeed, my SPI port was set as Master and to Ignore SS. Interestingly M(3), which is the SS pin, must be set as an Input in the DDRM for the SPI to function correctly. If M(3) is set as an output (i.e. DDRM bit 3 set to a 1), the SPI MOSI and the SCK never change state, however, all of the SPI0 status registers appear to give correct values. It is almost as if setting bit 3 of the DDRM affects the MODRR pin in that it appears as if the SPI is no longer connected to the Port M pins. Anyway, now that I know of this issue it no longer affects my design. However, I wanted to give others a "heads up" in case they run into this issue. Cheers, Sam ----- Original Message ----- From: "Zolt Ksi" <zoltan@zolt...> To: <68HC12@68HC...> Sent: Thursday, December 01, 2005 3:01 PM Subject: Re: [68HC12] SPI Bug (undocumented) on 9S12DG128B - Mask 0L85D >> Here is an undocumented SPI Bug that I came across yesterday... >> >> Device: MC9S12DG128BCFU (80 pin QFP) (Mask 0L85D) >> SPI Port: SPI0 >> Problem: The SPI0 pins/system becomes clobbered when the Data >> direction register associated with the shared SPI pins is set (in >> particular when Bit 3 is set). >> >> According to the SPI spec, once the SPI is enabled (and MODRR is set >> correctly), the associated shared I/O pins and I/O registers have no >> effect on these pins. Sadly, this is not the case. Setting Bit 3 of >> the DDRM (Port M pins are shared with SPI0) stops the SPI0 from >> working. > > Assuming that your SPI is in master mode, did you set it into ignore SS? > Otherwise if SS (port M(3)) is programmed as input and it is pulled low > (or floating at low) then your SPI will signal mode fault and stop. > Details are in the SPI manual. > > Zoltan > > > Yahoo! Groups Links > >

> Here is an undocumented SPI Bug that I came across yesterday... > > Device: MC9S12DG128BCFU (80 pin QFP) (Mask 0L85D) > SPI Port: SPI0 > Problem: The SPI0 pins/system becomes clobbered when the Data > direction register associated with the shared SPI pins is set (in > particular when Bit 3 is set). > > According to the SPI spec, once the SPI is enabled (and MODRR is set > correctly), the associated shared I/O pins and I/O registers have no > effect on these pins. Sadly, this is not the case. Setting Bit 3 of > the DDRM (Port M pins are shared with SPI0) stops the SPI0 from > working. Assuming that your SPI is in master mode, did you set it into ignore SS? Otherwise if SS (port M(3)) is programmed as input and it is pulled low (or floating at low) then your SPI will signal mode fault and stop. Details are in the SPI manual. Zoltan

Good day Everyone! Here is an undocumented SPI Bug that I came across yesterday... Device: MC9S12DG128BCFU (80 pin QFP) (Mask 0L85D) SPI Port: SPI0 Problem: The SPI0 pins/system becomes clobbered when the Data direction register associated with the shared SPI pins is set (in particular when Bit 3 is set). According to the SPI spec, once the SPI is enabled (and MODRR is set correctly), the associated shared I/O pins and I/O registers have no effect on these pins. Sadly, this is not the case. Setting Bit 3 of the DDRM (Port M pins are shared with SPI0) stops the SPI0 from working. Cheers, Sam