On May 4, 6:45=A0pm, "digitalforfun"
<yshali.shetty@n_o_s_p_a_m.gmail.com> wrote:
> Hello,
> I am using DLP FPGA kit which contains FT2232D chip. Data transfer is
> through parallel FIFO interface and D2xx driver. I have to transfer 3 byt=
es
> of data which is generated at different data rate in different
> scenarios.This 3 bytes of data is generated at X/Y rate in FPGA . Here X
> can have value of 5MHz, 7.5Mhz, 10 Mhz, 15MHz or 20 Mhz and Y will have
> value 256, 128 or 64.
>
> But while reading through application i am seeing data corruption in few
> samples. Earlier i was using Driver CDM 2.04.6 in which many samples were
> getting corrupted. In the application i had Settimer which has counter of
> 100 ms.So continuously every 100 ms i was reading the samples . To avoid
> the data corruption in the application i used to Reset after reading 2048=
0
> bytes using command "FT_ResetDevice".But even in this 20480, first 750
> samples will be corrupted .but always For option X/64 and X/128 data was
> corrupted after 10240 samples
>
> main()
> { SetTimer(15,100, NULL)}
>
> void CCStatsDlg::OnTimer(UINT nIDEvent)
> {
> status =3D GetQueueStatus(&bytes_in_buf);
> if(bytes_in_buf)
> {
> status =3D Read(rx, bytes_in_buf<20480 ? bytes_in_buf : 20480, &ret_bytes=
);
> if((status =3D=3D FT_OK) || ((status =3D=3D FT_IO_ERROR) && (ret_bytes > =
0)) /*
> Read timeout */)
> {
> if(ret_bytes)
> {
> UpdateData(TRUE);
>
> for(DWORD x=3D0; x<20480; x++)
> {
> if(rx[x] =3D=3D 0xff)
> {
>
> temp_output=3D 64*rx[x+2]+rx[x+1];
> fprintf(fp_write,"%d\n",temp_output);
>
> }
>
> Now i have upgraded the driver to CDM2.08.14 .Now data corruption is less
> frequent but still present.
>
> The state machine for TXE and RXF in FPGA looks ok for me. So not sure wh=
at
> is the problem..
>
> Any suggestion?
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.EmbeddedRelated.com

<rant>
My experience with the FTDI provided (windows) drivers, especially the
ones for the FIFO interface, leads me assert that they would have to
improve a great deal before they merely sucked.  "Usually" is not a
term that should be included in a "status valid" column.

A while back I sent them a 12-line "C" program that showed that the
value returned by a status call was wrong, and there was no indication
that it was wrong (until you guessed that it returned a valid status,
and the PC hung).

The response I got was "yes, so what's your point?"  Translated to
North American English that's "Too hard to fix, and the pub's open."
</rant>

Move to Linux, roll your own driver, or change chips.  I did #1 and
#3.

YMMV (hopefully),
RK

Hello,
I am using DLP FPGA kit which contains FT2232D chip. Data transfer is
through parallel FIFO interface and D2xx driver. I have to transfer 3 bytes
of data which is generated at different data rate in different
scenarios.This 3 bytes of data is generated at X/Y rate in FPGA . Here X
can have value of 5MHz, 7.5Mhz, 10 Mhz, 15MHz or 20 Mhz and Y will have
value 256, 128 or 64.

But while reading through application i am seeing data corruption in few
samples. Earlier i was using Driver CDM 2.04.6 in which many samples were
getting corrupted. In the application i had Settimer which has counter of
100 ms.So continuously every 100 ms i was reading the samples . To avoid
the data corruption in the application i used to Reset after reading 20480
bytes using command "FT_ResetDevice".But even in this 20480, first 750
samples will be corrupted .but always For option X/64 and X/128 data was
corrupted after 10240 samples

main()
{ SetTimer(15,100, NULL)}


void CCStatsDlg::OnTimer(UINT nIDEvent)
{
status = GetQueueStatus(&bytes_in_buf);
if(bytes_in_buf)
{
status = Read(rx, bytes_in_buf<20480 ? bytes_in_buf : 20480, &ret_bytes);
if((status == FT_OK) || ((status == FT_IO_ERROR) && (ret_bytes > 0)) /*
Read timeout */)
{
if(ret_bytes)
{
UpdateData(TRUE); 

for(DWORD x=0; x<20480; x++)
{ 
if(rx[x] == 0xff)
{

temp_output= 64*rx[x+2]+rx[x+1];
fprintf(fp_write,"%d\n",temp_output);
}

Now i have upgraded the driver to CDM2.08.14 .Now data corruption is less
frequent but still present.

The state machine for TXE and RXF in FPGA looks ok for me. So not sure what
is the problem..

Any suggestion? 

	   
					
---------------------------------------		
Posted through http://www.EmbeddedRelated.com