>You've answered your own question....
>
>> but as there is the bus arbiter, it was suposed to work...
>
>
>> the FPGA started to burst write to to the computer and never stoped.
>
>
>The arbiter can't arbitrate if a device doesn't respond to it.
>
>
>Nial. 
>
>
>

No sorry was not clear. I am using the OC PCI Bridge, and my mistake was on
the Wishbone line... so basicaly the PCI will behave ok but will try to get
the mastership constantly, but it does stop if the arbiter deny it.....	  

					
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You've answered your own question....

> but as there is the bus arbiter, it was suposed to work...


> the FPGA started to burst write to to the computer and never stoped.


The arbiter can't arbitrate if a device doesn't respond to it.


Nial. 

Hi, i am implementing a PCI card using a FPGA. I am performing my
tests on an old Pentium III computer that is basically fully based on
the PCI bus. The OS is Linux. It is all working fine incluiding
mastering but something weird happened today. I made a mistake at my
FPGA code and at some point the FPGA started to burst write to to the
computer and never stoped. I was controlling the computer using a
notebook using SSH and when that problem happened the computer just
hanged, i could not do anything. So my question is, when i master a
PCI bus, does the CPU get involved at any point on this transaction.
The computer could get hanged becouse i was using the whole PCI
bandwidth, but as there is the bus arbiter, it was suposed to work...
I guess the same happen with the memory access... So any idea why that
happened? As far as i understand the CPU does not perform instruction
related to the PCI bus when i am mastering it right?

Thank you!