Allan Herriman wrote:
> On Fri, 02 Sep 2011 17:46:44 -0500, Vladimir Vassilevsky wrote:
> 
> 
>>It turns out that switching regulators can generate significant ripple
>>at the output for the brief moment when the external sync signal is
>>applied or removed.
>>
>>Sometimes that caused mysterios result which was very difficult to trace
>>to the cause.
>  
> 
> I like to sync up my DC/DC converters to the same clock to improve the 
> input current waveform.  The synchronisation happens shortly after power 
> is applied, typically sourced from an oscillator that runs from a rail 
> supplied from the output of one of the POL DC/DC converters that is being 
> synchronised.
> 
> This all happens well before the system reset is released.  I've never 
> observed any issues with it.

I generated sync by dividing system clock in FPGA; that's why it caused 
   problems.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

On Fri, 02 Sep 2011 17:46:44 -0500, Vladimir Vassilevsky wrote:

> It turns out that switching regulators can generate significant ripple
> at the output for the brief moment when the external sync signal is
> applied or removed.
> 
> Sometimes that caused mysterios result which was very difficult to trace
> to the cause.


I like to sync up my DC/DC converters to the same clock to improve the 
input current waveform.  The synchronisation happens shortly after power 
is applied, typically sourced from an oscillator that runs from a rail 
supplied from the output of one of the POL DC/DC converters that is being 
synchronised.

This all happens well before the system reset is released.  I've never 
observed any issues with it.

Regards,
Allan

It turns out that switching regulators can generate significant ripple 
at the output for the brief moment when the external sync signal is 
applied or removed.

Sometimes that caused mysterios result which was very difficult to trace 
to the cause.


Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com