Hi All,

I am seeking clarification of the SPI slave operation for the LPC2138

When an LPC2138 is configured as a slave.
Please assume the SPI control register has been configured correctly
for slave  eg:
    bit2 BitEnable= 0 (SPI set to 8bit size)
    bit3 CPHA (set same as master)
    bit4 CPOL (set same as master)
    bit5 MSTR = 0 (set as slave)
    bit6 LSBF (set same as master)
    bit7 SPIE =1 (interupt enabled)
    bits8-15 not touched

QUESTIONs
Q1
The slave SPI S0SPDR is bidirectional  -separate Tx and Rx buffer
(eg like  a SPI master and UARTs -- separate Tx and Rx buffers) -
correct? Please advise.

Q2.1
When the master writes to the LPC2138 slave SPI, the SPI slave just
clocks out what has been written to S0SPDR previously  AND is
independant on what it has recieved from the SPI master- correct?
Please advise.

Q2.2
For the LPC2138 Slave  - what data is clocked out if nothing is
written to S0SPDR previous AND for ongoing SPI transactions?

Is the same S0SPDR in the SPI repeatly transmitted if not written too?

Q3
When writing to the LPC2138 SPI slave SSEL must be active low for the
whole SPI transaction... ie for one or multiple bytes (words)
transmitted  AND the end of the byte (words) is determined by the
number of clocks and not by deactivating the SSEL (to High).

Q4
There is quite a bit more detial on the SPI for Philips LPC900 8bit
80c51 core micro's...  does the LPC2000 series share a similar SPI h/w
structure?

COMMENT / REQUEST
---------------
The block diagrm of the SPI h/w in the LPC2138 UM isn't detialed
enough to show the logic sequencing...

Does anyone have a detailed block diagram on the SPI - a picture tells
a thousand words..
	I look forward to any replies and responses.
	Regards
Joe G