> Everything works in the FPGA, PCI read/write
> transactions, but we cannot achieve full line rate
> for 64-byte frame length. We can only achieve
> 680Mbps because of the overhead in reading/writing
> descriptors.
Have you tried your tests with much larger packets? Say, 1500 bytes?
Classic Ethernet has a mandatory Inter-Frame Gap (IFG) which results in
more overhead for smaller packets. This is likely an artifact of shared
hub usage - it may not have been carried forward into the Gig-E specs.
In general, it is common for networking products to be rated by
throughput (at maximum packet sizes) and packet rate (measured at
minimum packet sizes).
Reply by owner●April 19, 20042004-04-19
This is somewhat OT - more on networking.
I am using a Gigabit Ethernet MAC chip from Marv***, which claims full
line rate (compliance to IEEE 802.3ab). It has an integrated GMAC,
PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we
connect it to a Spartan IIe-300 with a Xilinx PCI Logicore.
Everything works in the FPGA, PCI read/write transactions, but we
cannot achieve full line rate for 64-byte frame length. We can only
achieve 680Mbps because of the overhead in reading/writing
descriptors.
My questions are: Is this expected? Is this acceptable? I have no
prior experience with Gigabit Ethernet MAC, and appreciates any
feedback.
Thanks
Kang Liat Chuan