Looks like you are well on track with your new project, but I
just wanted to correct a misconception: the "now extinct HC12 processor" is not extinct at all! It has simply been renumbered. This was done a few years ago to a number of chips, during the RoHS phase-in:

MC68HC812A4CPV8 became MC812A4CPVE8
MC68HC912B32CFU8 became MCHC912B32CFUE8
MC68HC912D60ACPV8 became MC912D60ACPVE8
etc.

These chips are currently in stock with many distributors.

In fact, very few HC12 chips are "extinct". Many are "not recommended for new design" but that has a whole different meaning.

Best regards,
Carl Barnes
www.technologicalarts.com
Q. What comes after "R"duino?
A. "S"duino, of course!
Check out Esduino, the new S12-based Arduino-compatible...

--- In 6..., drranu@... wrote:
>
> Hi all,
>
> I successfully designed and realized a project using a now extinct HC12 processor back in 2003, so I am now trying to use the 9S12DJ64 to take its place. I have two questions:
>
> 1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz crystal (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7 driven low, VDDPLL bypassed to GND with 100nF. The PLL components across XFC and VDPLL (using the Motorola filter application) are 2.7kohm in series with 4.7nF and those in parallel with a 470pF. However, my 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM, so I suspect the 9S12DJ64 oscillator is not functioning. Is there anything I should look out for? I don't need the PLL actually, so if I can get the 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.
>
> 2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a 68HC912B32 eval board (also running at 8 MHz bus) with D-Bug12?
>
> Thank you.
>

Edward,

Thanks for checking the schematic. I went ahead and bought a BDM board from Technological Arts with D-Bug12. Hopefully that will solve the problem.
--- In 6..., "Edward Karpicz" wrote:
>
> Circuit looks ok. Though docs say that MODA and MODB are pulled low
> internally while RESET is pulled low, I prefer not to trust weak internal
> pull ups here. But I guess this is not what causes your problems.
>
> I also have doubts if old dBug for HC12B32 supports S12D64 or not. It wasn't
> updated since 2000. dBug that runs on 9S12Dx256 and 9S12Dx128 certainly
> supports D64 and all old HC12 families.
>
> Edward
>
> ----- Original Message -----
> From: "aaronbige"
> To: <6...>
> Sent: Sunday, June 27, 2010 23:43
> Subject: [68HC12] Re: 9S12DJ64 oscillator and BDM question
> > Hi Edward,
> >
> > I really appreciate your responding.
> >
> > Test is grounded. VDD1 and 2 are bypassed to ground via 220nF caps.
> > VDDPLL is bypassed to ground with 100nF (and connected to the PLL
> > passives). VRGEN is pulled up to 5V and bypassed to ground with 100nF.
> >
> > You can find the schematic for my (very simple) application here:
> > 9S12DJ64 Schematic
> > > > chematic.png>
> >
> > I do understand that without a PLL the crystal will need to be twice the
> > bus freq. I have a 16 MHz crystal at the ready if I decide to go with
> > the Colpitts, but I thought I could use the flexibility of the PLL and
> > Pierce. And for programming, since my only BDM interface is through the
> > 68HC912B32 eval board D-Bug12 running at 8 MHz bus, I will need to leave
> > my 9S12DJ64 at 8 MHz bus too whilst I debug my code.
> >
> > Thanks!
> >
> > --- In 6..., "Edward Karpicz" wrote:
> >>
> >> Is voltage regulator enabled? (Is VREGEN pulled up to 5V (VDDR,
> > VDDX)?)
> >> Is TEST tied to VSS?
> >> Make sure VDD1, VDD2 and VDDPLL have NO connection to 5V VDDR and
> > VDDX.
> >> VDD1,VDD2 and VDDPLL should be powered from internal voltage regulator
> > and
> >> should be bypassed to closest VSS with >= 0.1uF.
> >>
> >> 8MHz crystal and no PLL means 4MHz bus clock, not 8MHz.
> >>
> >> Edward
> >>
> >> ----- Original Message -----
> >> From:
> >> To: <6...>
> >> Sent: Sunday, June 27, 2010 5:32 PM
> >> Subject: [68HC12] 9S12DJ64 oscillator and BDM question
> >>
> >>
> >> > Hi all,
> >> >
> >> > I successfully designed and realized a project using a now extinct
> > HC12
> >> > processor back in 2003, so I am now trying to use the 9S12DJ64 to
> > take its
> >> > place. I have two questions:
> >> >
> >> > 1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz
> > crystal
> >> > (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7
> >> > driven low, VDDPLL bypassed to GND with 100nF. The PLL components
> > across
> >> > XFC and VDPLL (using the Motorola filter application) are 2.7kohm in
> >> > series with 4.7nF and those in parallel with a 470pF. However, my
> >> > 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM,
> > so I
> >> > suspect the 9S12DJ64 oscillator is not functioning. Is there
> > anything I
> >> > should look out for? I don't need the PLL actually, so if I can get
> > the
> >> > 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.
> >> >
> >> > 2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a
> > 68HC912B32
> >> > eval board (also running at 8 MHz bus) with D-Bug12?
> >> >
> >> > Thank you.
> >> >
> >> >
> >> >
> >> >
> >> >

Circuit looks ok. Though docs say that MODA and MODB are pulled low
internally while RESET is pulled low, I prefer not to trust weak internal
pull ups here. But I guess this is not what causes your problems.

I also have doubts if old dBug for HC12B32 supports S12D64 or not. It wasn't
updated since 2000. dBug that runs on 9S12Dx256 and 9S12Dx128 certainly
supports D64 and all old HC12 families.

Edward

----- Original Message -----
From: "aaronbige"
To: <6...>
Sent: Sunday, June 27, 2010 23:43
Subject: [68HC12] Re: 9S12DJ64 oscillator and BDM question
> Hi Edward,
>
> I really appreciate your responding.
>
> Test is grounded. VDD1 and 2 are bypassed to ground via 220nF caps.
> VDDPLL is bypassed to ground with 100nF (and connected to the PLL
> passives). VRGEN is pulled up to 5V and bypassed to ground with 100nF.
>
> You can find the schematic for my (very simple) application here:
> 9S12DJ64 Schematic
> > chematic.png> I do understand that without a PLL the crystal will need to be twice the
> bus freq. I have a 16 MHz crystal at the ready if I decide to go with
> the Colpitts, but I thought I could use the flexibility of the PLL and
> Pierce. And for programming, since my only BDM interface is through the
> 68HC912B32 eval board D-Bug12 running at 8 MHz bus, I will need to leave
> my 9S12DJ64 at 8 MHz bus too whilst I debug my code.
>
> Thanks!
>
> --- In 6..., "Edward Karpicz" wrote:
>>
>> Is voltage regulator enabled? (Is VREGEN pulled up to 5V (VDDR,
> VDDX)?)
>> Is TEST tied to VSS?
>> Make sure VDD1, VDD2 and VDDPLL have NO connection to 5V VDDR and
> VDDX.
>> VDD1,VDD2 and VDDPLL should be powered from internal voltage regulator
> and
>> should be bypassed to closest VSS with >= 0.1uF.
>>
>> 8MHz crystal and no PLL means 4MHz bus clock, not 8MHz.
>>
>> Edward
>>
>> ----- Original Message -----
>> From:
>> To: <6...>
>> Sent: Sunday, June 27, 2010 5:32 PM
>> Subject: [68HC12] 9S12DJ64 oscillator and BDM question
>> > Hi all,
>> >
>> > I successfully designed and realized a project using a now extinct
> HC12
>> > processor back in 2003, so I am now trying to use the 9S12DJ64 to
> take its
>> > place. I have two questions:
>> >
>> > 1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz
> crystal
>> > (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7
>> > driven low, VDDPLL bypassed to GND with 100nF. The PLL components
> across
>> > XFC and VDPLL (using the Motorola filter application) are 2.7kohm in
>> > series with 4.7nF and those in parallel with a 470pF. However, my
>> > 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM,
> so I
>> > suspect the 9S12DJ64 oscillator is not functioning. Is there
> anything I
>> > should look out for? I don't need the PLL actually, so if I can get
> the
>> > 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.
>> >
>> > 2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a
> 68HC912B32
>> > eval board (also running at 8 MHz bus) with D-Bug12?
>> >
>> > Thank you.
>> >
>> >
>> >
>> >
>> >

Hi Edward,

I really appreciate your responding.

Test is grounded. VDD1 and 2 are bypassed to ground via 220nF caps.
VDDPLL is bypassed to ground with 100nF (and connected to the PLL
passives). VRGEN is pulled up to 5V and bypassed to ground with 100nF.

You can find the schematic for my (very simple) application here:
9S12DJ64 Schematic
chematic.png>

I do understand that without a PLL the crystal will need to be twice the
bus freq. I have a 16 MHz crystal at the ready if I decide to go with
the Colpitts, but I thought I could use the flexibility of the PLL and
Pierce. And for programming, since my only BDM interface is through the
68HC912B32 eval board D-Bug12 running at 8 MHz bus, I will need to leave
my 9S12DJ64 at 8 MHz bus too whilst I debug my code.

Thanks!

--- In 6..., "Edward Karpicz" wrote:
>
> Is voltage regulator enabled? (Is VREGEN pulled up to 5V (VDDR,
VDDX)?)
> Is TEST tied to VSS?
> Make sure VDD1, VDD2 and VDDPLL have NO connection to 5V VDDR and
VDDX.
> VDD1,VDD2 and VDDPLL should be powered from internal voltage regulator
and
> should be bypassed to closest VSS with >= 0.1uF.
>
> 8MHz crystal and no PLL means 4MHz bus clock, not 8MHz.
>
> Edward
>
> ----- Original Message -----
> From:
> To: <6...>
> Sent: Sunday, June 27, 2010 5:32 PM
> Subject: [68HC12] 9S12DJ64 oscillator and BDM question
> > Hi all,
> >
> > I successfully designed and realized a project using a now extinct
HC12
> > processor back in 2003, so I am now trying to use the 9S12DJ64 to
take its
> > place. I have two questions:
> >
> > 1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz
crystal
> > (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7
> > driven low, VDDPLL bypassed to GND with 100nF. The PLL components
across
> > XFC and VDPLL (using the Motorola filter application) are 2.7kohm in
> > series with 4.7nF and those in parallel with a 470pF. However, my
> > 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM,
so I
> > suspect the 9S12DJ64 oscillator is not functioning. Is there
anything I
> > should look out for? I don't need the PLL actually, so if I can get
the
> > 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.
> >
> > 2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a
68HC912B32
> > eval board (also running at 8 MHz bus) with D-Bug12?
> >
> > Thank you.
> >
> >
> >
> >
> >

Is voltage regulator enabled? (Is VREGEN pulled up to 5V (VDDR, VDDX)?)
Is TEST tied to VSS?
Make sure VDD1, VDD2 and VDDPLL have NO connection to 5V VDDR and VDDX.
VDD1,VDD2 and VDDPLL should be powered from internal voltage regulator and
should be bypassed to closest VSS with >= 0.1uF.

8MHz crystal and no PLL means 4MHz bus clock, not 8MHz.

Edward

----- Original Message -----
From:
To: <6...>
Sent: Sunday, June 27, 2010 5:32 PM
Subject: [68HC12] 9S12DJ64 oscillator and BDM question
> Hi all,
>
> I successfully designed and realized a project using a now extinct HC12
> processor back in 2003, so I am now trying to use the 9S12DJ64 to take its
> place. I have two questions:
>
> 1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz crystal
> (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7
> driven low, VDDPLL bypassed to GND with 100nF. The PLL components across
> XFC and VDPLL (using the Motorola filter application) are 2.7kohm in
> series with 4.7nF and those in parallel with a 470pF. However, my
> 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM, so I
> suspect the 9S12DJ64 oscillator is not functioning. Is there anything I
> should look out for? I don't need the PLL actually, so if I can get the
> 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.
>
> 2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a 68HC912B32
> eval board (also running at 8 MHz bus) with D-Bug12?
>
> Thank you.
>

Hi all,

I successfully designed and realized a project using a now extinct HC12 processor back in 2003, so I am now trying to use the 9S12DJ64 to take its place. I have two questions:

1) I am using a Pierce oscillator on my 9S12DJ64 with an 8 MHz crystal (R_BM, with coupling caps into EXTAL and XTAL both at 22pF), PE7 driven low, VDDPLL bypassed to GND with 100nF. The PLL components across XFC and VDPLL (using the Motorola filter application) are 2.7kohm in series with 4.7nF and those in parallel with a 470pF. However, my 68HC912B32 eval board will not take control of my 9S12DJ64 via BDM, so I suspect the 9S12DJ64 oscillator is not functioning. Is there anything I should look out for? I don't need the PLL actually, so if I can get the 9S12DJ64 running at 8 MHz bus without it, I'd be pleased.

2) Can an 8 MHz bus 9S12DJ64 be controlled via the BDM by a 68HC912B32 eval board (also running at 8 MHz bus) with D-Bug12?

Thank you.