--- In , "jackson_cp" <jackson_cp@y...> wrote:
> I am using MC68HC11F1 in a project. But I am
facing siome problem
> in getting started with hardware interface and programing.
>
> I am using JBug11 to communicate with the chip.
> How I can interface External SRAM to MC68HC11F1.
> What to do with OE and WE\ pins of SRAM. If I am using Jbug11
> which all lines have to be connected to interface with SRAM.
>
> How i can download a program in .s19 format to the exrernal SRAM
> and How i can execute it.
Adding external memory to a HC11F1 is quite easy, since the 'F1
provides a non-multiplexed bus (no 'HC373/573 address latch
required) and also provides up to 4 firmware-programmable chip
selects for memory-mapped devices.
About the only extra hardware you will require - other than the
RAM/ROM device(s) themselves, is a small bit of glue logic to
generate the -OE (-RD) and -WE (-WR) signals that most static memory
devices require.
It is my preference (although, perhaps, not absolutely required) to
use a 3 NAND gate approach to create these signals. I would attempt
to create a ASCII graphic of the suggested schematic here, but the
Yahoo message formatter would likely distort it, so I will provide a
point-to-point wiring list instead.
Parts needed: One (1) 74HC00 quad NAND gate.
3 of the 4 NAND gates in this package will be used. I will refer to
the individual gates by letter - Gate A,B,C and D.
Gate A input 1 (pin 1) to HC11 E-clock output (pin 4)
Gate A input 2 (pin 2) to HC11 RW output (pin 5)
Gate A output (pin 3) is -OE (-RD) signal for memory.
Gate B is not used - tie its inputs (pins 4 and 5) to ground.
Gate C input 1 (pin 9) to HC11 E-clock output (pin 4)
Gate C input 2 (pin 10) to Gate D output (pin 11)
Gate C output (pin 8) is -WE (-WR) signal for memory.
Gate D inputs 1 & 2 (pins 12 & 13) to HC11 RW output (pin 5)
Gate D output (pin 11) to Gate C input 2 (pin 10)
Gate D is used to invert the HC11 RW signal.
Here's a schematic - it will probably get clobbered, but I'll try
anyway:
. 74HC00
. 1 _____
.E ----o--| \ 3
. | | A |o-----> -RD
.RW --o-|--|_____/
. | | 2
. | |
. | | 9 _____
. | o--| \ 8
. | | C |o-----> -WR
. | o--|_____/
. | |10
. | o--------------o
. | 12 _____ |
. o----| \ 11 |
. | | D |o---o
. o----|_____/
. 13
.
. 4 _____
. o----| \ 6
. | | B |o-----
. o----|_____/
. | 5
. _|_
. - Gnd
--------------------
If you intend to use both RAM and ROM/(E)EPROM/FLASH in your design,
use the F1's PG7 (CSPROG) output as the chip select (-CE/-CS) signal
for the ROM device, and PG6 (CSGEN) for the RAM chip select. If you
will only be adding external RAM, use PG7/CSPROG as the chip select.
It would not be a bad idea to add 4.7K pull-down resistors on pins
PG7 (20) and PG6 (21) if you are using it. Doing this will ensure
that the external memory that is selected by these pins will stay de-
selected when the 'F1 is reset into a non-external-bus mode (e.g.
bootstrap or single chip). Note, however, that if you do run
the 'F1 in single-chip or bootstrap mode, and attempt to use PG7 (or
PG6, if it is being used as a chip select) as general-purpose I/O,
you might inadvertently enable the data bus on the RAM and/or ROM,
which will be connected to Port C - furthermore, if you do have two
(or more) memory devices on the bus, it is possible that you might
enable both for output at the same time - not a good thing. If you
are using any of the Port G lines for chip selects, avoid using
these as general-purpose I/O in single-chip mode. Initialize them
to the inactive (typically LOW) level in your code, and leave them
alone afterward.
For more information on the F1's programmable chip select subsystem,
read section 4.5 of the MC68HC11F1 Technical Reference. After
reading this, if you have any further questions, feel free to ask.
Once you have your RAM (and/or other memory devices) connected, you
can read/write to it using JBug. Since JBug requires that you start
up in Bootstrap mode (and hence, with the external bus disabled) you
will need to change some JBug settings to enable the external bus.
Go to JBug's configuration dialog under the general tab, and check
the 'Alter HPRIO on reboot' checkbox. Enter the value 'E5'
in the
space provided ('Byte to send:'). You should also set the 'common
chip defaults' to the 'F1 setting. Once JBug has started, and has
uploaded the talker to your board, the HPRIO register will be
changed to a setting that will enable the external memory bus
(assuming you use the suggested value of $E5 for the HPRIO
setting). At this point, the external memory will be addressable by
the HC11, and JBug can be used to read/write/load/save from/to it.
Oh, one more thing about JBug settings - you will need to add a
entry to the text box labelled 'RAM' under the 'Memory Map'
tab of
the configuration dialog. If you have mapped your RAM to addresses
$8000-$FFFF, add a line that looks like this:
External RAM00..FFFF
If the mapping of your RAM is different, simply replace the
addresses shown above with the appropriate ones for your
configuration.
You might find that you will have to (manually) change the setting
of the CSSTRH, CSCTL, CSGADR and CSGSIZ registers from their post-
reset defaults to get all of your memory devices working properly.
The post-reset defaults should be OK if you are using a single
memory device controlled by the CSPROG (PG7) chip select. I usually
use a JBug AUTOSTART macro to automatically modify these registers
following a reboot on my 'F1 projects.
Any code you write should, of course, initialize the aforementioned
registers as part of its init routine.
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