Thank you all.
I'm start using SPI to connect to an MMC card.
Then maybe using a FAT file system.
Any sugestions or comments?
Regards.
--- In l..., "yagfk" wrote:
>
> --- In l..., "theothervmax" wrote:
> >
> > --- In l..., "r_goncalves2000"
wrote:
> > >
> > > Hi, I'm start using the SPI interface and I have a doubt.
> > > I'm using a LPC2294 with a 15MHz crystal.
> > > PLL factor is set to 4 and VPDIV is set to 1.
> > > So PCLK is 60MHZ.
> > > With these setings is the maximum SPI clock rate equal to 60MHz
/ 8 =
> > > 7,5MHz?
> >
> > You are absolutely right, the maximum is 7.5 MHz.
> >
> The last weeks I was testing around with spi-speed.
> As an base i used Martin Thomas ADC-prog with winarm.Here are the
> results,the comments are partly in german,because they were only ment
> to remember me later wat's done
> /***********************************************************************
> * ADCconfig.h
>
************************************************************************/
>
> #include "lpc21xx.h"
> #include "config.h"
> #include "uart.h"
>
>
>
> /* Voltage at V_ddA/V3A (LPC2129 Pin7) */
> /* connected to 3,3V on LPC-P2129 */
> #define VREF 33/10
>
> // The following are for the Olimex LPC-P2129 TESTER Board
> // Port Bit Definitions & Macros: Description - initial conditions
> #define TXD0_BIT BIT(0) // used by UART0
> #define RXD0_BIT BIT(1) // used by UART0
> #define P30_UNUSED_BIT BIT(30) // P0.30 unused - low output
>
> #define PIO_INPUT_BITS (uint32_t) ( \
> SW1_BIT | \
> SW2_BIT | \
> 0 )
>
> #define PIO_ZERO_BITS (uint32_t) ( \
> P30_UNUSED_BIT | \
> 0 )
>
> static void systemInit(void)
> {
> // --- enable and connect the PLL (Phase Locked Loop) ---
> // a. set multiplier and divider
> PLLCFG = MSEL | (1<
> // b. enable PLL
> PLLCON = (1<
> // c. feed sequence
> PLLFEED = PLL_FEED1;
> PLLFEED = PLL_FEED2;
> // d. wait for PLL lock (PLOCK bit is set if locked)
> while (!(PLLSTAT & (1<
> // e. connect (and enable) PLL
> PLLCON = (1<
> // f. feed sequence
> PLLFEED = PLL_FEED1;
> PLLFEED = PLL_FEED2;
>
> // --- setup and enable the MAM (Memory Accelerator Module) ---
> // a. start change by turning of the MAM (redundant)
> MAMCR = 0;
> // b. set MAM-Fetch cycle to 3 cclk as recommended for >40MHz
> MAMTIM = MAM_FETCH;
> // c. enable MAM
> MAMCR = MAM_MODE;
>
> // --- set VPB speed ---
> VPBDIV = VPBDIV_VAL;
>
> // --- map INT-vector ---
> #if defined(RAM_RUN)
> MEMMAP = MEMMAP_USER_RAM_MODE;
> #elif defined(ROM_RUN)
> MEMMAP = MEMMAP_USER_FLASH_MODE;
> #else
> #error RUN_MODE not defined!
> #endif
>
> PINSEL0 = 0x5500;
> PINSEL1 = 0x2A8; /* !!(for LPC 2124 only)LPC2106 only one SPI-0 ! */
> PINSEL2 = 0x00; /* P1.16 - 31 as GPIO */
>
> /* Set pclk to the same as cclk */
> VPBDIV = 0x1;
>
> /* Set to highest speed for SPI at 10 Mhz -> 1.25 Mhz,=3,6 sec*/
> /* lt Datasheet max 0x8 erlaubt,0x4und 0x2 geht aber noch !?! -0x6 =>
> 2.5 sec */
> /* !! nur 0x8 zeigt bei ADC-DAC einwandfreie Kurven !! */
> S0SPCCR = 0x8; //4 => 1,8 sec;2 => 0,9 sec aber nicht sicher
> S1SPCCR = 0x8; // ob phase erhaupt noch ok-0x6 noch Kompromiss,aber
> odd div??
>
> /* Device selected as master */
> S0SPCR = 0x24; // bit3 is H,means Data sampled on 2nd edge of clk
> S1SPCR = 0x24; //bit 4 is 0,means clock is activ high,Data ok at
> fallg. edge
> //CPOL = aktiv low,means at trailing edge is Data valid
>
>
> }and an second h-file:
>
> /* System Config */
>
> /*
> PLL
>
> - Main clock F_OSC=14,7MHz @ Olimex LPC-P2129) [limits: 10 MHz to
> 25 MHz]
> - System should run at max. Frequency (60MHz) [limit: max 60 MHz]
> - Choose multiplier M=4
> so cclk = M * F_OSC= 4 * 14745000Hz = 58980000 Hz
> - MSEL-Bits in PLLCFG (bits 0-4) MSEL = M-1
> - F_CCO must be inbetween the limits 156 MHz to 320 MHz
> datasheet: F_CCO = F_OSC * M * 2 * P
> - choose devider P=2 => F_CCO = 14745000Hz * 4 * 2 * 2
> = 235920000 ~=236 MHz
> - PSEL0 (Bit5 in PLLCFG) = 1, PSEL1 (Bit6) = 0 (0b01)
> */
> #define FOSC 14745000
> #define PLL_M 6 // x6 entspr. 88,470 MHz !!,tuts sogar mit SPI!(x7
> negativ !)
> #define MSEL (PLL_M-1)
> #define PSEL0 5
> #define PSEL1 6
>
> #define PLLE 0
> #define PLLC 1
>
> #define PLOCK 10
>
> #define PLL_FEED1 0xAA
> #define PLL_FEED2 0x55
>
>
> /*
> MAM(Memory Accelerator Module)
> - choosen: MAM fully enabled = MAM-Mode 2
> - System-Clock cclk=59MHz -> 3 CCLKs are proposed as fetch timing
> */
> #define MAM_MODE 2
> #define MAM_FETCH 3
>
> /*
> VPB (V... Pheriphal Bus)
> - choosen: VPB should run at full speed -> devider VPBDIV=1
> => pclk = cclk = 59MHz
> */
> #define VPBDIV_VAL 1
>
> /*
> SCB
> */
> #define MEMMAP_BOOT_LOADER_MODE 0 // Interrupt vectors are
> re-mapped to Boot Block.
> #define MEMMAP_USER_FLASH_MODE (1<<0) // Interrupt vectors are not
> re-mapped and reside in Flash.
> #define MEMMAP_USER_RAM_MODE (1<<1) // Interrupt vectors are
> re-mapped to Static RAM.
>
> Not to make the answer too long,the adc.c listing is not sent yet,also
> there would be jpg-pictures from the oszillograms,but here is no way
> to add them
>