"Subroto Datta" <sdatta@altera.com> wrote in message news:<Sv_5c.26205

snipping
> 
> The original poster asked for a schematic editor, to enter schematics along
> with predefined symbols for ALU's registers etc.  Just to make sure there is
> no confusion, the Quartus Schematic editor (aka Block Editor) is a different
> application from the RTL viewer. This is your classical schematic editor
> which allows you to place symbols which are predefined or created on the
> fly, in place editor node names, create busses and hook up the ports ....
> 
> The purpose of the RTL viewer is to allow the user to get a visual
> description/understanding of the logic generated during RTL synthesis by
> Quartus. It requires that the design has been processed by quartus_map i.e.
> the synthesis application. The contents of the RTL viewer cannot be modified
> or saved into a file. The RTL viewer is not available in the Free Web
> Edition.
> 
> 
> - Subroto Datta
> Altera Corp.

Does Quartus schematic allow a symbol that is already in place in a
schematic to have its self edited, ie can I add more ports to the
symbol while viewing it or does it require a new symbol view window to
reedit the symbol out of place. In a heavy schematic use environment,
this one difference makes it 10x more work if its not present.

2nd 
Can you ever see allowing what I and Ray have asked for, that is to
edit the RTL viewer with the changes only to placement and wire shapes
as hints so the next regeneration uses those hints if available for
the next draw.

Again with out that, the tool is almost useless.

I suspect that most RTL viewers come mostly from one little company in
Germany, I see them at DAC. They had some interest in this idea but I
didn't pursue it.

regards

johnjakson_usa_com

Francisco Camarero wrote:
> 
> Hello !
> 
> We are an academic institution teaching our students VLSI design, from FPGA
> to full custom ASIC. We have put great value on teaching VHDL during the
> past years with very good results from our students.
> 
> However, we have the impression that these students have difficulties
> working with  schematics as tools to document and express their
> architectural ideas, in part because we did not provide them with such a
> schematic edition tool and thus, we are currently thinking about adding
> such a tool to our design flow.
> 
> Among the requirements that we have collected for such a tool would be:
> 
> - real schematic edition tool, and not just a drawing tool, i.e:
>    - recognizes and keep the connectivity
>    - understands connectors and inversion bubbles
>    - can select whole nets and name them
>    - is able to work with hierarchical schematics
>    - makes a graphic difference between scalars and vectors (buses)
>   
> - available for different plattforms: Wintel, Linux, Mac OSX
> 
> - from the cost viewpoint, affordable by students, i.e: no high-end tool
> 
> - a library with block level (adder, multiplier, ALU, registers, datapath 
>   elements, memory, etc.) symbols is available, or can easily be buit.
>   
> - the tool must be able to netlist any schematic hierarchy into a VHDL
>   skeleton with entities declaration, instantiation statements and
>   architecture templates so that it support the VHDL code writing.
> 
> Any suggestions?
>   
>   
> Fran

Try HDL Designer from www.mentor.com

I use it with my students, and my company use it too. It is just great 
and very low cost for uducational. You will pay $500 by year for a 
complet package. But still stay expensive for company.

Students learn both VHDL and structural design. In first step, the 
student learn system logic, using prededined VHDL graphical cell (mux, 
and , counter, adder, filter, flip-flop, ALU, register bank ...). Then 
student learn VHDL and do their own cell or mini-core implementation 
like UART with FIFOs, SPDIF decoder and encoder ...

Laurent
www.hevs.ch , the school
www.amontec.com , my company

john jakson wrote:

> I asked these tool vendors to allow the end user to accept edits at
> least for placement of instances and then to remember those as hints.
> But they always regenerate them from scratch.

I agree that having savable viewer options would be useful.
However, not having to draw the boxes and wires is the main thing.
I don't want to do graphical editing, I just want to have a look.

> If I used the schematic tools, they write the crappiest HDL they can
> so its the lesser of 2 evils.

Yes. The code's the thing. Simulation waveforms
can make up for the HDL's lack of graphical hints.

> The other issue I now see is that even the perfect schematic tool with
> perfect written Verilog netlist would now have nother problem, I would
> want it to write out the Verilog in a precise format and or to write
> out a cycle equivalent version in C line by line equivalent. Thats
> really asking too much.

For me, a schematic is not the source, but a view of the source.
If I were to overwrite code from this view, the schematic
would become the source document.

   -- Mike Treseler

That said, it would be nice if the RTL viewer had an edit option that would
allow the user to move the blocks around to make the output more presentable.
I'm not talking about reconnecting the wires or changing the logic at all, just
an editor that allowed the schematics to be rearranged so that they could be
used in the documentation of a design.


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:865ab498.0403161137.2c4c5358@posting.google.com...
> "Kevin Neilson" wrote:
> > The best of both worlds is to do all the design in HDL, and then use a
tool
> > like Synplify's "HDL Analyst" to look at a schematic version of the
> > synthesized code.  Using Synplify one can see either the RTL or
structural
> > schematic.
>
> I agree with Kevin.
> It is a good thing to look at the rtl/netlist schematics.
> But let the computer draw them for you.
> Note that QuartusII ver 4.0 also includes an rtl viewer.
>
>   -- Mike Treseler

The original poster asked for a schematic editor, to enter schematics along
with predefined symbols for ALU's registers etc.  Just to make sure there is
no confusion, the Quartus Schematic editor (aka Block Editor) is a different
application from the RTL viewer. This is your classical schematic editor
which allows you to place symbols which are predefined or created on the
fly, in place editor node names, create busses and hook up the ports ....

The purpose of the RTL viewer is to allow the user to get a visual
description/understanding of the logic generated during RTL synthesis by
Quartus. It requires that the design has been processed by quartus_map i.e.
the synthesis application. The contents of the RTL viewer cannot be modified
or saved into a file. The RTL viewer is not available in the Free Web
Edition.


- Subroto Datta
Altera Corp.

mike_treseler@comcast.net (Mike Treseler) wrote in message news:<865ab498.0403161137.2c4c5358@posting.google.com>...
> "Kevin Neilson" wrote: 
> > The best of both worlds is to do all the design in HDL, and then use a tool
> > like Synplify's "HDL Analyst" to look at a schematic version of the
> > synthesized code.  Using Synplify one can see either the RTL or structural
> > schematic.
> 
> I agree with Kevin. 
> It is a good thing to look at the rtl/netlist schematics.
> But let the computer draw them for you.
> Note that QuartusII ver 4.0 also includes an rtl viewer.
> 
>   -- Mike Treseler

The only problem with that is that those schematics are total ____ for
anything but the simpleste cells. If you have more than a dozen items,
the tools have absolutely no sence of repetition.

If a kid see a dozen identical items labeled 0 to n in a pile of
others, they might place them in a straight line, but these idiot
renderers will splat them any old place becuase they have no concept
of regularitiy combining with control, they treat all instances as
equals.

I asked these tool vendors to allow the end user to accept edits at
least for placement of instances and then to remember those as hints.
But they always regenerate them from scratch.

In the real world it is often neccesary to write HDL in a perverse way
to find the best performance the synthesis will create, and that means
creating awkward instance hierarchies. I am stuck with pen & paper.

If I used the schematic tools, they write the crappiest HDL they can
so its the lesser of 2 evils.

FWIW, the best schematic tool I ever used was Compass tools for VLSI,
very Macish, quite dated goin back 20yrs but truelly an awesome SW and
very much gone. It allowed true edit in place of symbols in the
context of a parent schematic making it 10x more productive than
regular PCB oriented trash like Veriworst. The reason why they got it
right is simple, the underlying code was exactly the same for all
tools, edit in place mask editer, schematic. A mask editer written as
badly as most schematic tools would be kicked out.

I looked at "Electronics Workbench" at the DAC show years ago, the
reps hadn't a clue what edit in place meant, they thought I was
talking of edit, in the place you are, on yer bum, so by that def,
they had it.

The other issue I now see is that even the perfect schematic tool with
perfect written Verilog netlist would now have nother problem, I would
want it to write out the Verilog in a precise format and or to write
out a cycle equivalent version in C line by line equivalent. Thats
really asking too much.

end of rant

CBFalconer <cbfalconer@yahoo.com> wrote in message news:<4057371F.6364CB4F@yahoo.com>...
> Subroto Datta wrote:
> > 
>  ... snip ...
> > 
> > A free version of the Tool can be downloaded at:
> > http://www.altera.com/education/univ/software/unv-software.html
> 
> No it can't.  That page says, in part:
> 
> "Contact your University Program liaison to obtain copies of these
> programs and a license to use them. You must be a student, 
> professor, or university staff member of a university that is a
> member of the Altera University program."
> 
> and please do not toppost.


Hello CB,

  The web page has a link to the Quartus Web Edition which is FREE,
and does not require you to be a student, preofessor or university
student :-)


- Subroto Datta
Altera Corp.

"Kevin Neilson" wrote: 
> The best of both worlds is to do all the design in HDL, and then use a tool
> like Synplify's "HDL Analyst" to look at a schematic version of the
> synthesized code.  Using Synplify one can see either the RTL or structural
> schematic.

I agree with Kevin. 
It is a good thing to look at the rtl/netlist schematics.
But let the computer draw them for you.
Note that QuartusII ver 4.0 also includes an rtl viewer.

  -- Mike Treseler

Subroto Datta wrote:
> 
... snip ...
> 
> A free version of the Tool can be downloaded at:
> http://www.altera.com/education/univ/software/unv-software.html

No it can't.  That page says, in part:

"Contact your University Program liaison to obtain copies of these
programs and a license to use them. You must be a student, 
professor, or university staff member of a university that is a
member of the Altera University program."

and please do not toppost.

-- 
Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>  USE worldnet address!

"Francisco Camarero" <nospam@nospam.com> wrote in message
news:4056A867.9351BC4D@nospam.com...
>
>
> Hello !
>
> We are an academic institution teaching our students VLSI design, from
FPGA
> to full custom ASIC. We have put great value on teaching VHDL during the
> past years with very good results from our students.
>
> However, we have the impression that these students have difficulties
> working with  schematics as tools to document and express their
> architectural ideas, in part because we did not provide them with such a
> schematic edition tool and thus, we are currently thinking about adding
> such a tool to our design flow.
>
> Among the requirements that we have collected for such a tool would be:
>
> - real schematic edition tool, and not just a drawing tool, i.e:
>    - recognizes and keep the connectivity
>    - understands connectors and inversion bubbles
>    - can select whole nets and name them
>    - is able to work with hierarchical schematics
>    - makes a graphic difference between scalars and vectors (buses)
>
> - available for different plattforms: Wintel, Linux, Mac OSX
>
> - from the cost viewpoint, affordable by students, i.e: no high-end tool
>
> - a library with block level (adder, multiplier, ALU, registers, datapath
>   elements, memory, etc.) symbols is available, or can easily be buit.
>
> - the tool must be able to netlist any schematic hierarchy into a VHDL
>   skeleton with entities declaration, instantiation statements and
>   architecture templates so that it support the VHDL code writing.
>
> Any suggestions?
>
>
> Fran

The best of both worlds is to do all the design in HDL, and then use a tool
like Synplify's "HDL Analyst" to look at a schematic version of the
synthesized code.  Using Synplify one can see either the RTL or structural
schematic.
-Kevin