Hi Ponnmozhi,
The BRAM in the FPGA is as standard SRAM.
SRAM can be used for storing instruction and data but also used for
creating caches.
The same BRAM can't be used for both cache and standard memory at the
same time.
They are seperate BRAMs.
ex.
Creating a 8kb of LMB memory requires 4 BRAM (VII,VIIPro,S3) or 16 BRAM
(V,VE,S2,S2E).
To create a 8kb of instruction caches requires 5 BRAM (VII,VIIPro,S3) or
18 BRAM (V,VE,S2,S2E).
I think that you can ignore the warnig fro Data2MEM. I will check with
the hotline guys.
Gan
ponnmozhi wrote:
>Hi,
>I am working on the spartanIIe FPGA and making use of the microblaze
>processor(EDK tool). My doubt is a very general one. basically the
>microblaze document says that cache in microblaze is implemented
>using Block RAM and on the other hand he also says that Block RAM can
>be made use of as a local on chip memory.
>If that is the case then my doubt is...-
>How can BRAM be used as a cache as well as an onchip memory?
>
>I ask this because, while making a design using 'Base System
Builder'
>in EDK Tool, I came across two fields, one was to enable cache &
>another to have local data & instruction memory(which obviously
>refers to BRAM). But while indicating the size of cache it says that
>BRAM resources of FPGA will be used for cache. Now, is it possible to
>have part of BRAM act as cache & the other part as local memory??
>I even tried exhausting the local memory size by making it 8KB(this
>is the total capacity of BRAM in spartanIIe) and enabled cache as
>well, but surprisingly i could generate the bitstream without
>encountering any errors. I got one warning though i.e.
>
>"WARNING:Data2MEM:47 - Not all BitLanes in
>ADDRESS_BLOCK 'bram_block_0' have BMM location constraints.
>Some data for this ADDRESS_BLOCK may have been lost during BIT file
>replacement."
>
>What does this warning mean?
>
>Could someone please explain how cache is implmented if not for BRAM??
>
>Waiting for your kind response,
>
>thanks,
>ponnmozhi.
>
>
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