Sorry this message sat in the queue for so long, by the way. (New members' messages get queued up until I approve them and unmoderate the poster. (This policy, although work for your moderator, has spared the list from numerous yahoogroups spammers who do not hesitate to join groups just to spam them.)) To Shibashish, I would hope the (terse) Circuit Cellar articles are mostly self-explanatory. The purpose of the VGA interface is to display bitmapped video using a couple of device pins and a handful of gates, via some austere-but-too-clever-by-half LFSR counters. It uses the XR16 processor's 16-entry PC-register-file to DMA a 16-bit word every 8 clocks or so and shifts out pixels on both clock edges, thereby displaying a bilevel bitmap, 576x455 bits (OK, strictly speaking, 560x455). This was the best I could do with 12 MHz fixed clocks and 32 KB on the original XS40 boards. By the way, for folks doing debugging and system-bring-up, a video display is a nice low pin count way to get information out of your SOC. Somewhere around here I have a cheap and cheerful on-chip-memory character oriented video display core using two 512 B BRAMs, one for a 32x16 frame buffer and one for a 96 entry ASCII char gen ROM. Here was my posting about it. http://groups.google.com/groups?selm=aljjq9%24u16%241%40slb7.atl.mindspring.net&oe=UTF-8 I'll try to find it and post it to fpgacpu.org, which has now gone a whole year w/o an update. Sorry, I've been so quiet, my energies have been fully focused working back in the software industry. Best wishes to all, Jan Gray, Gray Research LLC

Need ideas regarding the following design: Design a pipeline writeback logic unit for a superscalar processor that would resolve in order write collisions and produce write enables to the register bank. Assume that the register bank consists of sixteen linearly addressed registers of sixteen bit width. The superscalar processor can execute a maximum of 6 instructions during a cycle. The execution unit consists of two ALUs each of which can produce 16 bit results during a cycle, two MACs each of which can produce a 16/32/40 bit results during a cycle, two load units each of which can fetch a 16/32/40/64 bit data, and two address generation units each of which can produce 16 bit results each. A sixteen bit data from any resource unit can be written to any register. 32 bit data can be written to odd-even pair, lower 16 bits should go to even numbered register. Writing 40-bit result can be considered similar to writing 32 bit result. 64 bit results can only be written to four consecutive registers beginning with an even numbered register. It is possible that during a cycle, an operation like bittest can occur in an execution unit and the results does not get updated in the general purpose register. Only instructions with write bits can write back to a register. The relevant pipeline details for the processor is as follows. AC1 Memory access 1 AC2 Memory access 2 EX Execution WB Write back The writeback logic may assumed to be run at 350 MHz in GS50. All computation units compute the result in EX. The time available for the results to write back to the registers is minimal, but there is enough time to meet setup time plus 4 levels of logic. The instructions can assumed to be executed as per the following grouping rules: ALU0 must have instruction assigned for ALU1 to be assigned an instruction Address unit 0 must have instruction assigned for address unit 1 to be assigned an instruction Equivalent procedure also works well with load unit and MAC unit . The inputs to the pipeline write back unit can include but not limited to the following, for each execution unit. These signals are valid in AC1. V : Instruction is valid and grouped TAG : 3-bit instruction tag RA : 4-bit Register destination Address W : Instruction modifies a register in ORF G : 0 - GPR, 1 Address registers SZ : 00 - Single, 01 - Double, 10 - Accumulator, 11 - quad word (word being 16 bits) It is possible that a mispredicted branch can flush the pipeline. Branch instruction is always grouped as the first instruction during a cycle. When flushing the pipeline, none of the instruction results can update the registers. For simplicity, assume only the results in the EX are flushed and the data in AC1 and AC2 are valid and would continue to roll down the pipeline. The writeback address and enables should appear at the register bank boundary in EX for the muxes to route the data into the destination register. ________________________________________________________________________ Yahoo! India Insurance Special: Be informed on the best policies, services, tools and more. Go to: http://in.insurance.yahoo.com/licspecial/index.html

----- Original Message ----- From: "shibashish patel" <> To: <> Cc: <> Sent: Monday, January 05, 2004 11:22 AM Subject: [fpga-cpu] Xsoc 16bit RISC > We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain the test-bench written for the same. IIRC it's a simple interface for a VGA monitor, to display low-resolution graphics and text. The parts act as a sort of DAC to generate the analogue values for the various colours and the components for the video signal are generated with VHDL. Leon -- Leon Heller, G1HSM Email: My low-cost Philips LPC210x ARM development system: http://webspace.webring.com/people/jl/leon_heller//lpc2104.html