Jan I've been using this for quite some time, with no problems. Here
is the init code snippet:
// Clear and enable FIFO, trig level 8
*(po->Ubase + FCR) = 0x87;
// Enable Rx interrupt
*(po->Ubase + IER) = 0x01;
When I get an Rx interrupt, I first get the IIR and mask with 0x0F.
0x00: Modem Status
0x06: Uart error
0x02: Transmitter FIFO empty
0x0C: Reciever FIFO stale (the one you deon't get)
0x04: Reciever FIFO at trig fill level
I then empty the reveiver FIFO in the ISR (until bit 0 in LSR is no
longer set). If I don't do that I may not get another reciever FIFO
stale interrupt.
Regards,
Lars Marmsater
--- In l..., Jan Thogersen wrote:
>
> Hi all,
>
> I'm playing with the uart fifo's on the LPC2148 and I have some
problems
> getting the receiver buffer timeout interrupt to
work. When I
disable
> the fifo the interrupt works just fine. I get the
interrupt when
the
> uart have received a new byte. However, when the fifo
i on I should
get
> an interrupt when the receiver times out.
> Maybe I haven't enabled the right interrupt...
> As far as I know, the processor should invoke an interrupt when the
> receiver fifo reached the trigger level, but also if it receives
lets
> say one byte and then none for a while.
> And it's this timeout I'm trying to get. Here is the way that I
> initializes the uart: U1IER = U1IER_RBR_Interrupt_Enable;
>
> Thanks in advance!
>
> Regards
> Jan
>
