Reply by Aleksandar Kuktin●December 20, 20142014-12-20
On Mon, 01 Dec 2014 14:30:12 +0000, Tim wrote:
> - non-volatile FPGA plus FTDI USB chip
> - connects to an Android host mode USB port
> - application software in Lua, with Java interface/driver
> - high-level Gideros software for whizzy graphics
> - FPGA firmware samples, including logic analyzer in source
>
> also works on a PC - useful for reprogramming the FPGA.
>
> Everything open source.
>
> www.bugblat.com/products/fan
Wait a minute, what exactly is this?
What am I - the user - capable of doing to the device with an Android?
Can I reprogram the FPGA? I assume yes, but do I need a PC for that? In
the sense "can I use only the Android phone to make a transition from
Verilog/VHDL sources to a programmed FPGA"?
Reply by rickman●December 10, 20142014-12-10
On 12/10/2014 9:36 AM, Tim wrote:
> On 06/12/2014 14:56, MK wrote:
>> I'm trying to get a couple of new ICE40 designs up and running (used an
>> 'HX1k before with no real trouble) and having problems with PLLs (trying
>> to simulate and also working out which pins the ref input can use -
>> Lattice say any GBIN but the ICECube tools says only two pins near the
>> PLL power pins). I was wondering if anyone has actually used the PLLs.
>> I'm also having no joy in getting slave spi mode to work (on 'HX4k) -
>> once again this was OK on the 1K part but there are still a few things
>> to try.
>>
>> Michael Kellett.
>>
>
> Does the ICE40 use the same hard macro as the XO2 and XO3?
I don't know for sure if the SPI design is the same or not. The ICE40
was not designed by Lattice. It was done by Silicon Blue which was
bought by Lattice a couple of years ago. Lattice made some tweaks to
the ICE40 line, but I doubt that they replaced the SPI port module with
their own.
> The XO2 slave SPI works well. We use it for configuration on our
> Raspberry Pi add-on board. We intended to use I2C, but the Pi cannot do
> I2C Restart so we had to fall back (!) to SPI for configuration.
>
> There's a clever hack to get I2C Restart to work on the Pi, but it
> relies on exact timing and jumping on the I2C bus at just the right
> moment. We passed on that.
>
> Pi I2C is just fine for regular (non-configuration) use where you can
> define a protocol that doesn't use Restarts.
>
> If it helps, our XO2 I2C code (VHDL) is here:
> https://github.com/bugblat/pif/blob/master/firmware/common/pifwb.vhd
>
> --
> Tim
>
--
Rick
Reply by Tim●December 10, 20142014-12-10
On 06/12/2014 14:56, MK wrote:
> I'm trying to get a couple of new ICE40 designs up and running (used an
> 'HX1k before with no real trouble) and having problems with PLLs (trying
> to simulate and also working out which pins the ref input can use -
> Lattice say any GBIN but the ICECube tools says only two pins near the
> PLL power pins). I was wondering if anyone has actually used the PLLs.
> I'm also having no joy in getting slave spi mode to work (on 'HX4k) -
> once again this was OK on the 1K part but there are still a few things
> to try.
>
> Michael Kellett.
>
Does the ICE40 use the same hard macro as the XO2 and XO3?
The XO2 slave SPI works well. We use it for configuration on our
Raspberry Pi add-on board. We intended to use I2C, but the Pi cannot do
I2C Restart so we had to fall back (!) to SPI for configuration.
There's a clever hack to get I2C Restart to work on the Pi, but it
relies on exact timing and jumping on the I2C bus at just the right
moment. We passed on that.
Pi I2C is just fine for regular (non-configuration) use where you can
define a protocol that doesn't use Restarts.
If it helps, our XO2 I2C code (VHDL) is here:
https://github.com/bugblat/pif/blob/master/firmware/common/pifwb.vhd
--
Tim
Reply by MK●December 7, 20142014-12-07
On 06/12/2014 15:08, rickman wrote:
> On 12/6/2014 9:56 AM, MK wrote:
>> On 05/12/2014 12:09, rickman wrote:
>>> On 12/2/2014 4:20 AM, MK wrote:
>>>> On 01/12/2014 14:30, Tim wrote:
>>>>> - non-volatile FPGA plus FTDI USB chip
>>>>> - connects to an Android host mode USB port
>>>>> - application software in Lua, with Java interface/driver
>>>>> - high-level Gideros software for whizzy graphics
>>>>> - FPGA firmware samples, including logic analyzer in source
>>>>>
>>>>> also works on a PC - useful for reprogramming the FPGA.
>>>>>
>>>>> Everything open source.
>>>>>
>>>>> www.bugblat.com/products/fan
>>>>>
>>>>> --
>>>>> Tim
>>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA
>>>> but I
>>>> think I'll buy one.
>>>> I'm really pleased to see the open source, VHDL, LUA and Android host -
>>>> nice combination.
>>>
>>> I think you sent me an email, although it may have been intended for the
>>> newsgroup. I tried to reply but the return address is bad and I can't
>>> seem to make it good.
>>>
>> Hello, I meant to post to the group but I'm forever clicking the wrong
>> button in Thunderbird. Sorry.
>>
>> I'm trying to get a couple of new ICE40 designs up and running (used an
>> 'HX1k before with no real trouble) and having problems with PLLs (trying
>> to simulate and also working out which pins the ref input can use -
>> Lattice say any GBIN but the ICECube tools says only two pins near the
>> PLL power pins). I was wondering if anyone has actually used the PLLs.
>> I'm also having no joy in getting slave spi mode to work (on 'HX4k) -
>> once again this was OK on the 1K part but there are still a few things
>> to try.
>
> I feel your pain with regards to T-bird. I seldom make that mistake now
> but at first it was a struggle.
>
> Keep us informed with your progress using the ICE40 parts. Maybe start
> a new thread.
>
> I am on Lattice's distribution list for EOL's and such. I just got a
> notice that they are deleting one of the two packages for the ultra
> parts. They say they had *no* design wins in the 20 pin package. I'm
> not entirely surprised with only 12 I/Os. They can't seem to find a
> middle ground.
>
> The emphasis for FPGAs seems to be more on package size than low pin
> count really. They don't go with any easier to use packages (read
> larger or non-BGA) with lower pin counts, but rather small packages
> regardless of pin count. I guess handheld is driving the market these
> days. Space is at a premium while I/O counts still need to be generous.
>
I'll try to post something on my web site - it needs some more
interesting new technical stuff.
Michael Kellett
Reply by rickman●December 6, 20142014-12-06
On 12/6/2014 9:56 AM, MK wrote:
> On 05/12/2014 12:09, rickman wrote:
>> On 12/2/2014 4:20 AM, MK wrote:
>>> On 01/12/2014 14:30, Tim wrote:
>>>> - non-volatile FPGA plus FTDI USB chip
>>>> - connects to an Android host mode USB port
>>>> - application software in Lua, with Java interface/driver
>>>> - high-level Gideros software for whizzy graphics
>>>> - FPGA firmware samples, including logic analyzer in source
>>>>
>>>> also works on a PC - useful for reprogramming the FPGA.
>>>>
>>>> Everything open source.
>>>>
>>>> www.bugblat.com/products/fan
>>>>
>>>> --
>>>> Tim
>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I
>>> think I'll buy one.
>>> I'm really pleased to see the open source, VHDL, LUA and Android host -
>>> nice combination.
>>
>> I think you sent me an email, although it may have been intended for the
>> newsgroup. I tried to reply but the return address is bad and I can't
>> seem to make it good.
>>
> Hello, I meant to post to the group but I'm forever clicking the wrong
> button in Thunderbird. Sorry.
>
> I'm trying to get a couple of new ICE40 designs up and running (used an
> 'HX1k before with no real trouble) and having problems with PLLs (trying
> to simulate and also working out which pins the ref input can use -
> Lattice say any GBIN but the ICECube tools says only two pins near the
> PLL power pins). I was wondering if anyone has actually used the PLLs.
> I'm also having no joy in getting slave spi mode to work (on 'HX4k) -
> once again this was OK on the 1K part but there are still a few things
> to try.
I feel your pain with regards to T-bird. I seldom make that mistake now
but at first it was a struggle.
Keep us informed with your progress using the ICE40 parts. Maybe start
a new thread.
I am on Lattice's distribution list for EOL's and such. I just got a
notice that they are deleting one of the two packages for the ultra
parts. They say they had *no* design wins in the 20 pin package. I'm
not entirely surprised with only 12 I/Os. They can't seem to find a
middle ground.
The emphasis for FPGAs seems to be more on package size than low pin
count really. They don't go with any easier to use packages (read
larger or non-BGA) with lower pin counts, but rather small packages
regardless of pin count. I guess handheld is driving the market these
days. Space is at a premium while I/O counts still need to be generous.
--
Rick
Reply by MK●December 6, 20142014-12-06
On 05/12/2014 12:09, rickman wrote:
> On 12/2/2014 4:20 AM, MK wrote:
>> On 01/12/2014 14:30, Tim wrote:
>>> - non-volatile FPGA plus FTDI USB chip
>>> - connects to an Android host mode USB port
>>> - application software in Lua, with Java interface/driver
>>> - high-level Gideros software for whizzy graphics
>>> - FPGA firmware samples, including logic analyzer in source
>>>
>>> also works on a PC - useful for reprogramming the FPGA.
>>>
>>> Everything open source.
>>>
>>> www.bugblat.com/products/fan
>>>
>>> --
>>> Tim
>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I
>> think I'll buy one.
>> I'm really pleased to see the open source, VHDL, LUA and Android host -
>> nice combination.
>
> I think you sent me an email, although it may have been intended for the
> newsgroup. I tried to reply but the return address is bad and I can't
> seem to make it good.
>
Hello, I meant to post to the group but I'm forever clicking the wrong
button in Thunderbird. Sorry.
I'm trying to get a couple of new ICE40 designs up and running (used an
'HX1k before with no real trouble) and having problems with PLLs (trying
to simulate and also working out which pins the ref input can use -
Lattice say any GBIN but the ICECube tools says only two pins near the
PLL power pins). I was wondering if anyone has actually used the PLLs.
I'm also having no joy in getting slave spi mode to work (on 'HX4k) -
once again this was OK on the 1K part but there are still a few things
to try.
Michael Kellett.
Reply by Tim●December 5, 20142014-12-05
On 04/12/2014 01:56, rickman wrote:
> On 12/3/2014 6:25 PM, Tim wrote:
>> On 03/12/2014 21:52, rickman wrote:
>>> On 12/3/2014 11:39 AM, Tim wrote:
>>>> On 02/12/2014 09:20, MK wrote:
>>>>> On 01/12/2014 14:30, Tim wrote:
>>>>>> - non-volatile FPGA plus FTDI USB chip
>>>>>> - connects to an Android host mode USB port
>>>>>> - application software in Lua, with Java interface/driver
>>>>>> - high-level Gideros software for whizzy graphics
>>>>>> - FPGA firmware samples, including logic analyzer in source
>>>>>>
>>>>>> also works on a PC - useful for reprogramming the FPGA.
>>>>>>
>>>>>> Everything open source.
>>>>>>
>>>>>> www.bugblat.com/products/fan
>>>>>>
>>>>>> --
>>>>>> Tim
>>>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA
>>>>> but I
>>>>> think I'll buy one.
>>>>> I'm really pleased to see the open source, VHDL, LUA and Android
>>>>> host -
>>>>> nice combination.
>>>>>
>>>>> Michael Kellett
>>>>
>>>> The ICE40 non-volatile memory is OTP. You can also program the SRAM
>>>> directly, but OTP is a problem in some applications.
>>>>
>>>> And this board is a spin-off from a bigger project, for which the
>>>> XO2 is
>>>> the best fit.
>>>
>>> Does the board have support for measuring power consumption of the XO2?
>>> Different rails?
>>>
>>
>> There's only one rail - 3.3V. This flavor of the XO2 has an internal
>> regulator for the core voltage.
>>
>> You can measure current draw by one of
>> - a USB current meter, easy to find on eBay
>> - lift the Schottky in the power input and replace with a 0.1R resistor.
>
> There is nothing on the board but the FPGA? Providing for power
> measurement takes more than just lifting a diode and adding a series
> resistor unless the FPGA is the only thing on the board. Also, even if
> there is not a separate core rail, the I/Os have their own power pins
> even if used at 3.3 volts in this design. These days many designs use
> other voltages.
>
>
>> As always, current consumption in an FPGA depends on the design it is
>> programmed with. But you know that.
>
> That is what I want to measure, the combination of part and design. I
> have an ICE40 board and would be interested in doing comparisons with
> the XO2. They talk about the XO2 having low power in some modes, but I
> expect it is nothing like the ICE40.
>
> I'm about to do some power measurements on the ICE40 I have. The
> original devices from Silicon Blue were specified as something around 30
> or 50 uA quiescent (can't remember off the top of my head). But they
> weren't really in production when Lattice took over and started dinking
> with the data sheet. They changed the quiescent from a max to a typ
> number and raised it to 100 uA for most in the family. I want to see
> *how* typical that number is and see just how much it goes up with a low
> power design. I get the impression the XO2 and XO3 may be competitive
> depending on that static/dynamic tradeoff.
>
There isn't much on the board - you can download the schematic and
check. Most of the components are various protection devices and they
should not affect the result, particularly if you do a comparison
against an unconfigured FPGA.
That would also remove th effect of the FTDI device.
A couple of config pins have pullups - not really needed because the
chip is programmed via JTAG - but you should be able to calculate their
current drain.
--
Tim
Reply by rickman●December 5, 20142014-12-05
On 12/2/2014 4:20 AM, MK wrote:
> On 01/12/2014 14:30, Tim wrote:
>> - non-volatile FPGA plus FTDI USB chip
>> - connects to an Android host mode USB port
>> - application software in Lua, with Java interface/driver
>> - high-level Gideros software for whizzy graphics
>> - FPGA firmware samples, including logic analyzer in source
>>
>> also works on a PC - useful for reprogramming the FPGA.
>>
>> Everything open source.
>>
>> www.bugblat.com/products/fan
>>
>> --
>> Tim
> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I
> think I'll buy one.
> I'm really pleased to see the open source, VHDL, LUA and Android host -
> nice combination.
I think you sent me an email, although it may have been intended for the
newsgroup. I tried to reply but the return address is bad and I can't
seem to make it good.
--
Rick
Reply by rickman●December 3, 20142014-12-03
On 12/3/2014 6:25 PM, Tim wrote:
> On 03/12/2014 21:52, rickman wrote:
>> On 12/3/2014 11:39 AM, Tim wrote:
>>> On 02/12/2014 09:20, MK wrote:
>>>> On 01/12/2014 14:30, Tim wrote:
>>>>> - non-volatile FPGA plus FTDI USB chip
>>>>> - connects to an Android host mode USB port
>>>>> - application software in Lua, with Java interface/driver
>>>>> - high-level Gideros software for whizzy graphics
>>>>> - FPGA firmware samples, including logic analyzer in source
>>>>>
>>>>> also works on a PC - useful for reprogramming the FPGA.
>>>>>
>>>>> Everything open source.
>>>>>
>>>>> www.bugblat.com/products/fan
>>>>>
>>>>> --
>>>>> Tim
>>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA
>>>> but I
>>>> think I'll buy one.
>>>> I'm really pleased to see the open source, VHDL, LUA and Android host -
>>>> nice combination.
>>>>
>>>> Michael Kellett
>>>
>>> The ICE40 non-volatile memory is OTP. You can also program the SRAM
>>> directly, but OTP is a problem in some applications.
>>>
>>> And this board is a spin-off from a bigger project, for which the XO2 is
>>> the best fit.
>>
>> Does the board have support for measuring power consumption of the XO2?
>> Different rails?
>>
>
> There's only one rail - 3.3V. This flavor of the XO2 has an internal
> regulator for the core voltage.
>
> You can measure current draw by one of
> - a USB current meter, easy to find on eBay
> - lift the Schottky in the power input and replace with a 0.1R resistor.
There is nothing on the board but the FPGA? Providing for power
measurement takes more than just lifting a diode and adding a series
resistor unless the FPGA is the only thing on the board. Also, even if
there is not a separate core rail, the I/Os have their own power pins
even if used at 3.3 volts in this design. These days many designs use
other voltages.
> As always, current consumption in an FPGA depends on the design it is
> programmed with. But you know that.
That is what I want to measure, the combination of part and design. I
have an ICE40 board and would be interested in doing comparisons with
the XO2. They talk about the XO2 having low power in some modes, but I
expect it is nothing like the ICE40.
I'm about to do some power measurements on the ICE40 I have. The
original devices from Silicon Blue were specified as something around 30
or 50 uA quiescent (can't remember off the top of my head). But they
weren't really in production when Lattice took over and started dinking
with the data sheet. They changed the quiescent from a max to a typ
number and raised it to 100 uA for most in the family. I want to see
*how* typical that number is and see just how much it goes up with a low
power design. I get the impression the XO2 and XO3 may be competitive
depending on that static/dynamic tradeoff.
--
Rick
Reply by Tim●December 3, 20142014-12-03
On 03/12/2014 21:52, rickman wrote:
> On 12/3/2014 11:39 AM, Tim wrote:
>> On 02/12/2014 09:20, MK wrote:
>>> On 01/12/2014 14:30, Tim wrote:
>>>> - non-volatile FPGA plus FTDI USB chip
>>>> - connects to an Android host mode USB port
>>>> - application software in Lua, with Java interface/driver
>>>> - high-level Gideros software for whizzy graphics
>>>> - FPGA firmware samples, including logic analyzer in source
>>>>
>>>> also works on a PC - useful for reprogramming the FPGA.
>>>>
>>>> Everything open source.
>>>>
>>>> www.bugblat.com/products/fan
>>>>
>>>> --
>>>> Tim
>>> Interesting - I'm slightly regretting you didn't use an ICE40 FPGA but I
>>> think I'll buy one.
>>> I'm really pleased to see the open source, VHDL, LUA and Android host -
>>> nice combination.
>>>
>>> Michael Kellett
>>
>> The ICE40 non-volatile memory is OTP. You can also program the SRAM
>> directly, but OTP is a problem in some applications.
>>
>> And this board is a spin-off from a bigger project, for which the XO2 is
>> the best fit.
>
> Does the board have support for measuring power consumption of the XO2?
> Different rails?
>
There's only one rail - 3.3V. This flavor of the XO2 has an internal
regulator for the core voltage.
You can measure current draw by one of
- a USB current meter, easy to find on eBay
- lift the Schottky in the power input and replace with a 0.1R resistor.
As always, current consumption in an FPGA depends on the design it is
programmed with. But you know that.
---
Tim