>
> Ooops,
>
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an
> inverter)
> needed to make an external crystal run can support 1-50 MHz, not
> the PLL.
> We did test the PLL below 10 MHz and it locked reliably at least
> down to 5 MHz. There were no thorough tests done below 5 MHz as
> this
> is already way out of spec. What we could see, the jitter
> increased
> a lot when using the PLL with 5 MHz input.
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with
> the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
>
> It is however correct that a lower external input frequency
> reduces
> the likelyhood of the startup problem to occur.
>
> nxp_apps
>

OK, Thanks,

These are some LPC2124 boards returned from customer... :(
I cannot change the circuit.
I will use 7.3Mhz fsoc, and wire a DIP8 WatchDog
Timer if I can find someway to "spider" it... :)

Regards

An Engineer's Guide to the LPC2100 Series

--- In l..., "Brendan Murphy"
> Regardless of how much testing you do, you clearly need to be aware
> that following this recommendation is ignoring specific information
> from NXP that problems have been seen with the PLL when the source
> clock is outside the specified range of 10-25 Mhz.

You clearly need to be aware that the objective specification and
recommended specifications to the end user can be very different.

Jaya

--- In l..., "jayasooriah"
wrote:
>
> --- In l..., "roger_lynx" wrote:
> > And if you were looking specifically for PLL jitter, where would
you
> > look at?
>
> Look at the eye pattern of any signal generated by MCU, for example
> PWM. You need to ensure you are not synchronising exactly on PLL
> divisor rate or it will appear jitter free. So if you are
dividing by
> 16, sync on every 17th pulse and you get the full eye pattern in
just
> 16 overlays.
>
> > When you say "sustained operation", do you mean over the entire
> > (specified) temp. range?
>
> Not in this case. When DUT was subjected to arbitrary frequency
and
> duty ratios down to 1MHz, I do not rememner any of the observations
> suggested that PLL capture failed. Thus I said it should work okay
> with 3.68 MHz crystal.
>
> I did not question the original information I got that said PLL
range
> is 1-50 MHz and that it is was specified to end user (in user
manuals)
> as 10-25 MHz.
>
> Now that NXP_apps has clarified that 1-50 MHz applies to
oscillator,
> not PLL, anyone planning to run with less than 10 MHz crystal
should
> do burn in tests to be sure.
>
> Jaya
>

Regardless of how much testing you do, you clearly need to be aware
that following this recommendation is ignoring specific information
from NXP that problems have been seen with the PLL when the source
clock is outside the specified range of 10-25 Mhz.

Brendan.

--- In l..., "roger_lynx" wrote:
> And if you were looking specifically for PLL jitter, where would you
> look at?

Look at the eye pattern of any signal generated by MCU, for example
PWM. You need to ensure you are not synchronising exactly on PLL
divisor rate or it will appear jitter free. So if you are dividing by
16, sync on every 17th pulse and you get the full eye pattern in just
16 overlays.

> When you say "sustained operation", do you mean over the entire
> (specified) temp. range?

Not in this case. When DUT was subjected to arbitrary frequency and
duty ratios down to 1MHz, I do not rememner any of the observations
suggested that PLL capture failed. Thus I said it should work okay
with 3.68 MHz crystal.

I did not question the original information I got that said PLL range
is 1-50 MHz and that it is was specified to end user (in user manuals)
as 10-25 MHz.

Now that NXP_apps has clarified that 1-50 MHz applies to oscillator,
not PLL, anyone planning to run with less than 10 MHz crystal should
do burn in tests to be sure.

Jaya

Hi Jaya,

And if you were looking specifically for PLL jitter, where would you
look at?

When you say "sustained operation", do you mean over the entire
(specified) temp. range?
I am curious.

Best regards
Roger

--- In l..., "jayasooriah" wrote:
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>

--- In l..., "jayasooriah" wrote:
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
Jaya,

that is an interesting data point. Would not have thought this works.
Thanks for this input.

Bob

--- In l..., "nxp_apps" wrote:

> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> needed to make an external crystal run can support 1-50 MHz, not the
> PLL.

You may be right that the 1-50 MHz was only for the crystal
oscillator. We ran devices at 1 MHz (for purposes I rather not
discuss) and while we were not looking specifically for PLL jitter,
the indications are that there were no problems with PLL capture or
sustained operation.

Jaya

> What is the story with these /00 chips (LPC2114,2119,2124,2129)?
They are
> only mentioned in the errata sheets, and it is hinted that they are
not the
> same as the "B" revision. Do they fix more bugs than "B", or even
add
> features like fast GPIO?
>
> Karl Olsen
>
Karl,

the /00s have only one fix, that is the startup, nothing else fixed.
We are working on /01 versions that have all the fixes and will
include new features like the fast I/Os

Hope the /01s will be out in 1st quarter 07

nxp_apps

---- Original Message ----
From: "nxp_apps"
To:
Sent: Thursday, October 19, 2006 5:04 PM
Subject: [lpc2000] Re: LPC2124's PLL working with 3.68Mhz fosc??

> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.

What is the story with these /00 chips (LPC2114,2119,2124,2129)? They are
only mentioned in the errata sheets, and it is hinted that they are not the
same as the "B" revision. Do they fix more bugs than "B", or even add
features like fast GPIO?

Karl Olsen

--- In l..., "jayasooriah"
wrote:
>
> --- In l..., "unity0724" wrote:
>
> > Hello!
> > I'm only interested in:
> > - Getting that LPC2124 reset problem fixed! (or minimized)
> > - Checking if LPC2124 PLL is stable with 3.68MHz fosc
> >
> > I Do NOT have any interest in the bootloader issue...
> > unless your bootloader is able to fix the LPC2124 reset
> > problem... :)
> >
> > And, Sorry, where is that "The PLL supports 1-50MHz" from?
> > I cannot find it from user manual.
> > Could only find: "The PLL accepts an input clock frequency
> > in the range of 10 MHz to 25 MHz only" from user manual.
> >
> > You happen to have another customer running the PLL below
> > 10Mhz??
> >
> > Regards
>
> I don't know what your reset problem is. I was only responding to
> your question alluded to by the title "PLL working with 3.68Mhz
fosc".
>
> I know that the PLL used in the LPC family is specified as 1-50
MHz.
> Therefore it will work at 3.68 MHz. I have seen it in working
outside
> the 10-25 MHz range.
>
> I am told that it was limited to 10-25 MHz in the user manual
because
> of boot loader support issues. I do not know what the issues are.
>
> I can say however that I have not had any problems with my boot
loader
> with the full 1-50 MHz range.
>
> Good luck.
>
> Jaya
>
Ooops,

I happen to know that the PLL is specified from 10-25 MHz input
only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
needed to make an external crystal run can support 1-50 MHz, not the
PLL.
We did test the PLL below 10 MHz and it locked reliably at least
down to 5 MHz. There were no thorough tests done below 5 MHz as this
is already way out of spec. What we could see, the jitter increased
a lot when using the PLL with 5 MHz input.
To get the reset problem fixed on the 2124, you actually need to
follow the instructions in the Errata Sheet, a double reset with the
given minimum time in between will fix it.

There is also a version LPC2124/00 which has the startup problem
fixed in hardware.

It is however correct that a lower external input frequency reduces
the likelyhood of the startup problem to occur.

nxp_apps