A Beaujean wrote:
> However, at reset, the CPU defaults to Little Endian mode. 
> 
> There comes then the issue of coherent switching from the Little to
> Big Endian mode.

I've got an old project that does this:

reset_vector:
    // set big-endian
    mrc   p15, 0, r0, c1, c0, 0
    orr   r0, r0, #0x80
    mcr   p15, 0, r0, c1, c0, 0
    CPWAIT  r0

YMMV

-- 
Michael N. Moran           (h) 770 516 7918
5009 Old Field Ct.         (c) 678 521 5460
Kennesaw, GA, USA 30144    http://mnmoran.org

"So often times it happens, that we live our lives in chains
  and we never even know we have the key."
The Eagles, "Already Gone"

The Beatles were wrong: 1 & 1 & 1 is 1

Having developed a new IXP425 based card, we now face the problem of
writing the BSP for it.

Actually, the main problem at this very moment is understanding the
real issues with Endianess.

Indeed, primary tests made with the ARM MultiIce emulator appear to
clearly indicate that Big Endian is required if wanting to access the
IXP425 expansion bus with correct addressing (bytewise or wordwise).

As known, the boot device(s) on the IXP425 CPU must be located on the
expansion bus. We selected 16 bits wide for the boot device.

However, at reset, the CPU defaults to Little Endian mode. 

There comes then the issue of coherent switching from the Little to
Big Endian mode.

More precisely :

A) Is the bootloader to be generated in Little or Big Endian ?
B) How to handle the copy to SDRAM (byte swapping or not) ?
C) How and when to switch Endian mode to constantly keep data
coherency ?

Is anyone aware of a good explanatory document dealing with the
problem, or better an example of a startup code ?

Your help will be greatly appreciated.

A. Beaujean