OK, found it.....
Didn't notice that FCR is a write-only register.
Using bitfield ops to set the FIFO reset bits was clearing the FIFO enable bit,
a setting that "must
not be used in the application..."
On Tue, 19 Dec 2006 20:32:13 +0000, you wrote:
>Having problems setting up UART receive interrupt on
LPC2103 (IAR, using J-Link)
>
>VIC is set up OK as int code is executing, but it is not clearing the
interrupt, so int code is
>getting executed continuously, despite no data actually being sent to it.
> IIR is showing to 0C, i.e. CTI int, but LSR bit 0 is clear, indicating no
data....
>The int occurs as soon as the UART interrupt is enabled,
>
>This should be getting cleared by reads from RBR in the int routine, but it
just isn't being....
>what am I doing wrong? This is driving me nuts now.....!
>
>I am not sending any data to the UART, and the RXD1 line is high.
>UART setup :
>
> U1LCR=3; // 8 bits
> U1LCR_bit.DLAB=1;
>
> U1DLL=4; // 250kbaud at FclkdMHz
> U1DLM=0;
> U1FDR_bit.DIVADDVAL=0;
> U1FDR_bit.MULVAL=0;
>
> U1FCR_bit.FCRFE=1;
> U1FCR_bit.RTLS=1; // 0 1 byte,01 4 bytes 02 8 bytes 03 14 bytes
> U1MCR=0;
> U1LCR_bit.DLAB=0;
>
> U1FCR_bit.TFR=1; // reset fifos
> U1FCR_bit.RFR=1;
> temp=U1RBR;
> U1IER=1; // RX interrupt only
> __enable_interrupt();
>
>// Int service :
>__irq __arm void uart1int(void)
>{
> volatile Int32U itemp;
> FIOSET=1; // debug flag
> itemp=U1IIR; // figure out source of int
> switch(itemp & 0x0f) {
>
> case 6 : // line status
> itemp=U1LSR; // get status & clear int
> break;
> case 12 : // character timeout (fifo empty)
> case 4 : // RX data available
> itemp=U1RBR; // get data, clear int - INT IS NOT GETTING CLEARED!!!
> break;
>
> case 2 : // Tx reg empty
> break;
>
> case 0 : // modem status
> itemp=U1MSR; // clear
> break;
>
>
> }
>
>
> itemp++;
>
> FIOCLR=1;
> VICVectAddr = 0; // dummy write to complete
interrupt cycle
>}
>
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