> Random opinions: > - I like Quartus II (Altera) a lot more than ISE, the > latter feels a lot less polished. > - The ML401 development kit (Xilinx) is hands-down the > best ~$500 development kit out there, but is _not_ > supported by the free ISE WebPACK :-( > - The new Stratix II has a really interesting > architecture. I'd love an ML401 with a Stratix II > instead of the Virtex4 (Altera? Xmas? Please? ;-) I would like to add one to Tommy's list from a production board standpoint: We continue to find that we cannot obtain Altera devices in same density; i.e. given a limited space (board requirement), the Xilinx part has more logic capacity in a smaller footprint. And, Xilinx seems to offer more range of devices to choose from for each footprint. For example, we put down an XC3S400-FG456, but we know we can move up to XC3S1000 or XC3S1500 if needed, without changing footprint. Every time we ask our Altera FAEs and reps to give us the equivalent Altera part for a given Xilinx part that will meet our requirements, they're silent. From salespeople, no news is bad news. In this situation, tools etc. become less relevant. You gotta be able to build the board and support it over time with new features. -Jeff

>> Martin Schoeberl wrote: >> JOP: a Java processor soft-core for FPGAs: http://www.jopdesign.com/ >> >> With this processor you can postbone your decision about A vs. X >> because it runns on both (e.g. Cyclone, Spartan-3). However, the design >> runns faster on the Cyclone than on the Spartan-3 (100MHz vs. 82MHz). >> >> > Can you please give your opinion on why you think that the JOP runs > faster on the Cyclone than the Spartan-3? I think it is just the fact that the Cyclone is a little bit faster than the Spartan-3. But I don't want to start a flame ware between C and S - we had discussions on this issue on comp.arch.fpga (where a guy from Altera wondered that JOP wasn't much more faster on the Cyclone ;-) Cyclone and Spartan-3 are comparable and competitive FPGAs. It depends on the application, which one is faster. For DSP applications I expect that the Spartan will be the winner as it contains hardware multiplier. However, I want to stress that I have no Altera or Xilinx optimized code in JOP. > > Is there a way to close this performance gap? > Not from the VHDL coding level. Perhaps Xilinx will add another speed grade for Spartan-3 (Cyclone comes in three grades, wheras Spartan-3 only in two) or you could squeeze out a few ps with floor-planning. Martin

Martin, > Martin Schoeberl wrote: > JOP: a Java processor soft-core for FPGAs: http://www.jopdesign.com/ > > With this processor you can postbone your decision about A vs. X > because it runns on both (e.g. Cyclone, Spartan-3). However, the design > runns faster on the Cyclone than on the Spartan-3 (100MHz vs. 82MHz). Can you please give your opinion on why you think that the JOP runs faster on the Cyclone than the Spartan-3? Is there a way to close this performance gap? What is your personal opinion on this issue? Richard Newman

Yes, You can do this in NIOS but you have to create two different versions, one for the custom instruction and one for the Avalon interfacing. With the FSL interfaces, you can connect it to the processor or connect it to a streaming interface from a memory controller or why not from your own HW logic. The actually idct module does not change at all. The key to acceleration is to connect it to the right place and if you want to move it around without changing the interface all the time, the FSL interface is a saver. Another key benefit of the FSL is that if I want to do a 2-D idct, I can chain two 1-D FSL modules together. One FSL module is feeding the other FSL module, this is hard to do with custom instructions since it's very tied to the processor. Gan James wrote: >In Nios II, I'd implement the IDCT as a coprocessor. The coprocessor >could connect to the Nios II CPU using custom instructions or using >Avalon (the on-chip interconnect fabric). > >In the custom instruction version, you have Nios II load the source >operands from memory, use a custom instruction to transfer two 32-bit >operands per cycle to the coprocessor, use a custom instruction to >start the operation, use a custom instruction to transfer one 32-bit >result value per cycle, and then use Nios II store instructions to >save the results to memory. You have to do the same thing with >Microblaze but the FSLs can only transfer one 32-bit value every >other cycle so Nios II would be significantly faster. > >However, if you really want the best performance, I'd make the IDCT >its own SOPC Builder component with an Avalon master interface. Think >of it as an intelligent DMA. Instead of having Nios II move around >source and result values, Nios II just provides the memory addresses >to the coprocessor (either through a custom instruction or an Avalon >slave interface) and then waits for it to complete. The IDCT reads >the source operands from memory, performs the computation, and writes >back the result. This provides the best speedup. > >+james+ > >--- In , Gan Bilski <goran.bilski@x> wrote: >>Hi, >> >>The custom function is attaching a full function on the FSL (fifo) >>channels that MicroBlaze has. >> >>Custom instruction has the drawback that you can only have 2 >> >> >operands >>and 1 result which minimize the usage of it. >>Most useful instruction are already covered by the ISA. >> >>One example that I use to demonstrate this is to optimize a idct >>function that is needed for a jpeg decoder. >>If you run a jpeg decoder, the idct function will take most of the >> >> >CPU >>cycles, >>Further more the idct function is a loop in a loop function as many >> >> >DSP >>functions are. >>The idct function has 8 inputs and 8 outputs and uses 64 constants >> >> >for >>the calculation. >>By examine the assembler output from the compiler and using custom >>instructions, you can create your own super MAC instructions which >> >> >not >>only does a MAC but also contains the whole constant table plus >>autoincrement the pointer into the constant table. >>If you get this instruction to execute in 1 clock cycle, you have >>increase the performance of the idct function with 90% which is not >> >> >a >>bad improvement. >> >>But if you take the FSL approach you place the WHOLE idct function >> >> >into >>HW and just pass the parameters through the FIFO and receive the >> >> >results >>through the FIFO. This will improve the performance 1010% which is >> >> >7x >>faster than the custom instruction. >>WHY? >>Because the whole function is placed in HW, you can collapse both >> >> >loops >>and there is where all the performance gain is. >>But in order to collapse the loops, you have now 8 inputs and 8 >> >> >outputs >>which is hard to specify in a custom instruction. >> >>The custom instruction sounds nice but doesn't really give you that >> >> >much >>gain. The FSL has potential of improving your application with 10x >> >> >or 100x. >>Gan >> >>Perez Ramas, Javier Basilio wrote: >> >> >> >>> Hello, >>> >>> >>> >>> >>> >>>>-----Mensaje original----- >>>>De: Gan Bilski [mailto:goran.bilski@x...] >>>>Enviado el: martes, 14 de diciembre de 2004 20:24 >>>>Para: >>>>Asunto: Re: [fpga-cpu] Xilinx vs Altera / Microblaze vs Nios??? >>>> >>>> >>>> >>>> >>>> >>>>>>* Nios II and Microblaze are roughly of the same architecture. >>>>>> >>>>>> >>>>>> >>>>>> >>>>>However, Nios II is more customizable and Microblaze cannot >>>>> >>>>> >handle >>>>>custom instructions (is this true) >>>>> >>>>> >>>>> >>>>> >>>>> >>>>> >>>>MicroBlaze can do much more by allowing you to do customer >>>> >>>> >functions >>>>which is far more powerful than custom instructions. >>>> >>>> >>>> >>>> >>> Please, can you explain further what do you want to say >>> >>> >with "customer functions"? >>> As far as I know, the ways to "expand" Microblaze is either >>> >>> >a custom OPB-connected hardware or hardware attached to a superlink >FIFO. Is this correct? Although that's valid for most applications I >think that the "custom opcodes" is really a powerful function. >>> Best regards, >>> >>> Javier Basilio Pez Ramas >>> GECOM sensors >>> INDRA Sistemas, S.A. >>> >>> >>>To post a message, send it to: >>>To unsubscribe, send a blank message to: fpga-cpu- >>> >> > >>>Yahoo! Groups Links >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> >> >To post a message, send it to: >To unsubscribe, send a blank message to: >Yahoo! Groups Links >

In Nios II, I'd implement the IDCT as a coprocessor. The coprocessor could connect to the Nios II CPU using custom instructions or using Avalon (the on-chip interconnect fabric). In the custom instruction version, you have Nios II load the source operands from memory, use a custom instruction to transfer two 32-bit operands per cycle to the coprocessor, use a custom instruction to start the operation, use a custom instruction to transfer one 32-bit result value per cycle, and then use Nios II store instructions to save the results to memory. You have to do the same thing with Microblaze but the FSLs can only transfer one 32-bit value every other cycle so Nios II would be significantly faster. However, if you really want the best performance, I'd make the IDCT its own SOPC Builder component with an Avalon master interface. Think of it as an intelligent DMA. Instead of having Nios II move around source and result values, Nios II just provides the memory addresses to the coprocessor (either through a custom instruction or an Avalon slave interface) and then waits for it to complete. The IDCT reads the source operands from memory, performs the computation, and writes back the result. This provides the best speedup. +james+ --- In , Gan Bilski <goran.bilski@x> wrote: > Hi, > > The custom function is attaching a full function on the FSL (fifo) > channels that MicroBlaze has. > > Custom instruction has the drawback that you can only have 2 operands > and 1 result which minimize the usage of it. > Most useful instruction are already covered by the ISA. > > One example that I use to demonstrate this is to optimize a idct > function that is needed for a jpeg decoder. > If you run a jpeg decoder, the idct function will take most of the CPU > cycles, > Further more the idct function is a loop in a loop function as many DSP > functions are. > The idct function has 8 inputs and 8 outputs and uses 64 constants for > the calculation. > By examine the assembler output from the compiler and using custom > instructions, you can create your own super MAC instructions which not > only does a MAC but also contains the whole constant table plus > autoincrement the pointer into the constant table. > If you get this instruction to execute in 1 clock cycle, you have > increase the performance of the idct function with 90% which is not a > bad improvement. > > But if you take the FSL approach you place the WHOLE idct function into > HW and just pass the parameters through the FIFO and receive the results > through the FIFO. This will improve the performance 1010% which is 7x > faster than the custom instruction. > WHY? > Because the whole function is placed in HW, you can collapse both loops > and there is where all the performance gain is. > But in order to collapse the loops, you have now 8 inputs and 8 outputs > which is hard to specify in a custom instruction. > > The custom instruction sounds nice but doesn't really give you that much > gain. The FSL has potential of improving your application with 10x or 100x. > > Gan > > Perez Ramas, Javier Basilio wrote: > > > Hello, > > > > > > > >>-----Mensaje original----- > >>De: Gan Bilski [mailto:goran.bilski@x...] > >>Enviado el: martes, 14 de diciembre de 2004 20:24 > >>Para: > >>Asunto: Re: [fpga-cpu] Xilinx vs Altera / Microblaze vs Nios??? > >> > >> > >> > >>>>* Nios II and Microblaze are roughly of the same architecture. > >>>> > >>>> > >>>However, Nios II is more customizable and Microblaze cannot handle > >>>custom instructions (is this true) > >>> > >>> > >>> > >>> > >>MicroBlaze can do much more by allowing you to do customer functions > >>which is far more powerful than custom instructions. > >> > >> > > > > Please, can you explain further what do you want to say with "customer functions"? > > > > As far as I know, the ways to "expand" Microblaze is either a custom OPB-connected hardware or hardware attached to a superlink FIFO. Is this correct? Although that's valid for most applications I think that the "custom opcodes" is really a powerful function. > > > > > > Best regards, > > > > Javier Basilio Pez Ramas > > GECOM sensors > > INDRA Sistemas, S.A. > > > > > >To post a message, send it to: > >To unsubscribe, send a blank message to: fpga-cpu- > >Yahoo! Groups Links > > > > > > > > > > > > > > > > > >

Mats and all, as this discussion is going more in the direction of soft-core processors I would like to add another option: JOP: a Java processor soft-core for FPGAs: http://www.jopdesign.com/ With this processor you can postbone your decision about A vs. X because it runns on both (e.g. Cyclone, Spartan-3). However, the design runns faster on the Cyclone than on the Spartan-3 (100MHz vs. 82MHz). This processor is open-source (all VHDL and Java sources are on the website) and free for educational purpose. JOP is perhaps more 'university-compatible' than Nios and MicroBlaze, as it was developed as part of a PhD thesis. There are several papers available about JOP. JOP is already used at universities for education and research. Martin ----- Original Message ----- From: "James" <> To: <> Sent: Wednesday, December 15, 2004 11:30 PM Subject: [fpga-cpu] Re: Xilinx vs Altera / Microblaze vs Nios??? > > > Mats, > > As the Nios II architect and designer, I'm excited that you are > interested in using a soft-core FPGA processor. > I wish I had one of these to play with when I was in university. > > I'll give you my opinions but also encourage you to contact Mike > Phipps (). > He is in charge of our university program and is open to granting > development boards and tools to universities. > > I also encourage you to to check out Nios Forum (www.niosforum.com). > This is the main user forum for Nios and Nios II users (mostly Nios > II). > It is on a web site sponsored by Altera but the content is not > controlled by Altera. > > As for Nios II vs. Microblaze, both are excellent implementations of > 32-bit RISC processors. Given your educational perspective, > comparisons of performance and/or size are probably not your most > important consideration. The Nios II custom instruction facility is > quite easy to use and very powerful. Custom instructions can either > be purely combinatorial or multicycle. I could easily imagine a lab > where students analyze an algorithm and create custom instructions to > accelerate it. You can call custom instructions from assembly code > or from C-code (they look like functions). You could also have > students create a custom coprocessor with its own Avalon master > interface to get larger performance gains albeit for more design > effort. > > If you want students to analyze or even modify the Nios II code, rest > assured that it is just standard VHDL/Verilog; we don't use any hand- > coded lookup table masks. > We rely on Quartus synthesis to produce the programming file for the > FPGA. > > As for a difference in tools, I believe we have the advantage. Our > main tools are Quartus, SOPC Builder, Nios II IDE, and the compiler > toolchain. SOPC Builder uses the Avalon interconnect to connect SOPC > Builder components including Nios II. Avalon was designed > specifically for the characteristics of FPGAs. SOPC Builder and Nios > II developed by the same Altera team and work very well together. > The IDE is based on the open source Eclipse framework and the > compiler toolchain is based on the open source gcc tools. > > Besides uCLinux, Nios II also has support for the eCos and uCOS-II > (Microtronix) operating systems. In fact, the Nios II kit comes > bundled with uCOS-II and comes with the associated book. All of these > operating systems include source code. There are other operating > systems available but I figure these are the most interesting to > educational users. > > As for your board needs, any of our Cyclone or Stratix Nios > development boards should satisfy your requirements. Our smallest > board has a 10,000 LE Stratix device which can easily accomodate 4 > Nios II CPUs and peripherals (e.g. sdram controller, pio, uart, > timer, ethernet). There are three versions of the Nios II core > ranging from an economy version that is 600 LEs to a high-performance > version that is 1800 LEs. > > I hope you find this information useful. > > James Ball > > --- In , "Mats Brorsson" <matsbror@i...> > wrote: >> >> >> We are in the process of selecting an FPGA board for a series of >> laborations in courses ranging from computer engineering, embedded >> software development to VHDL design, SoC architectures and > operating >> systems. >> >> We are trying to evaluate Xilinx vs Altera boards and the > Microblaze >> vs Nios II processors against each other. My first own overall >> impression is: >> >> * Xilinx is more often used in universities than Altera >> * Altera's development tools seems to be a little more intuitive >> than Xilinx' >> * Nios II and Microblaze are roughly of the same architecture. >> However, Nios II is more customizable and Microblaze cannot handle >> custom instructions (is this true) >> * Both Altera and Xilinx can offer about the same IP-cores to >> supplement the soft cores >> * uCLinux is ported for both Microblaze and NiosII >> >> Any comments on which one to prefer and why? We have previously > been >> using Altera but are in a position to switch to Xilinx now if > needed. >> >> I also need suggestions on development board to choose. >> >> I am overwhelmed with the large number of development boards >> available for both Altera's and Xilinx' devices. We'd need a board >> with the following capabilities: >> * a device that could host a design with 4 soft-cores and some >> peripherals >> * some DRAM (>4 Mbyte) >> * some useful I/O-connections >> (e.g. Ethernet, USB, PS/2, VGA) >> * some basic I/O devices >> (e.g. LEDS, buttons and DIP-switches) >> >> Any suggestions? >> >> Sincerely >> >> Mats Brorsson > To post a message, send it to: > To unsubscribe, send a blank message to: > Yahoo! Groups Links > >

Mats, As the Nios II architect and designer, I'm excited that you are interested in using a soft-core FPGA processor. I wish I had one of these to play with when I was in university. I'll give you my opinions but also encourage you to contact Mike Phipps (). He is in charge of our university program and is open to granting development boards and tools to universities. I also encourage you to to check out Nios Forum (www.niosforum.com). This is the main user forum for Nios and Nios II users (mostly Nios II). It is on a web site sponsored by Altera but the content is not controlled by Altera. As for Nios II vs. Microblaze, both are excellent implementations of 32-bit RISC processors. Given your educational perspective, comparisons of performance and/or size are probably not your most important consideration. The Nios II custom instruction facility is quite easy to use and very powerful. Custom instructions can either be purely combinatorial or multicycle. I could easily imagine a lab where students analyze an algorithm and create custom instructions to accelerate it. You can call custom instructions from assembly code or from C-code (they look like functions). You could also have students create a custom coprocessor with its own Avalon master interface to get larger performance gains albeit for more design effort. If you want students to analyze or even modify the Nios II code, rest assured that it is just standard VHDL/Verilog; we don't use any hand- coded lookup table masks. We rely on Quartus synthesis to produce the programming file for the FPGA. As for a difference in tools, I believe we have the advantage. Our main tools are Quartus, SOPC Builder, Nios II IDE, and the compiler toolchain. SOPC Builder uses the Avalon interconnect to connect SOPC Builder components including Nios II. Avalon was designed specifically for the characteristics of FPGAs. SOPC Builder and Nios II developed by the same Altera team and work very well together. The IDE is based on the open source Eclipse framework and the compiler toolchain is based on the open source gcc tools. Besides uCLinux, Nios II also has support for the eCos and uCOS-II (Microtronix) operating systems. In fact, the Nios II kit comes bundled with uCOS-II and comes with the associated book. All of these operating systems include source code. There are other operating systems available but I figure these are the most interesting to educational users. As for your board needs, any of our Cyclone or Stratix Nios development boards should satisfy your requirements. Our smallest board has a 10,000 LE Stratix device which can easily accomodate 4 Nios II CPUs and peripherals (e.g. sdram controller, pio, uart, timer, ethernet). There are three versions of the Nios II core ranging from an economy version that is 600 LEs to a high-performance version that is 1800 LEs. I hope you find this information useful. James Ball --- In , "Mats Brorsson" <matsbror@i...> wrote: > > > We are in the process of selecting an FPGA board for a series of > laborations in courses ranging from computer engineering, embedded > software development to VHDL design, SoC architectures and operating > systems. > > We are trying to evaluate Xilinx vs Altera boards and the Microblaze > vs Nios II processors against each other. My first own overall > impression is: > > * Xilinx is more often used in universities than Altera > * Altera's development tools seems to be a little more intuitive > than Xilinx' > * Nios II and Microblaze are roughly of the same architecture. > However, Nios II is more customizable and Microblaze cannot handle > custom instructions (is this true) > * Both Altera and Xilinx can offer about the same IP-cores to > supplement the soft cores > * uCLinux is ported for both Microblaze and NiosII > > Any comments on which one to prefer and why? We have previously been > using Altera but are in a position to switch to Xilinx now if needed. > > I also need suggestions on development board to choose. > > I am overwhelmed with the large number of development boards > available for both Altera's and Xilinx' devices. We'd need a board > with the following capabilities: > * a device that could host a design with 4 soft-cores and some > peripherals > * some DRAM (>4 Mbyte) > * some useful I/O-connections > (e.g. Ethernet, USB, PS/2, VGA) > * some basic I/O devices > (e.g. LEDS, buttons and DIP-switches) > > Any suggestions? > > Sincerely > > Mats Brorsson

Hi, The custom function is attaching a full function on the FSL (fifo) channels that MicroBlaze has. Custom instruction has the drawback that you can only have 2 operands and 1 result which minimize the usage of it. Most useful instruction are already covered by the ISA. One example that I use to demonstrate this is to optimize a idct function that is needed for a jpeg decoder. If you run a jpeg decoder, the idct function will take most of the CPU cycles, Further more the idct function is a loop in a loop function as many DSP functions are. The idct function has 8 inputs and 8 outputs and uses 64 constants for the calculation. By examine the assembler output from the compiler and using custom instructions, you can create your own super MAC instructions which not only does a MAC but also contains the whole constant table plus autoincrement the pointer into the constant table. If you get this instruction to execute in 1 clock cycle, you have increase the performance of the idct function with 90% which is not a bad improvement. But if you take the FSL approach you place the WHOLE idct function into HW and just pass the parameters through the FIFO and receive the results through the FIFO. This will improve the performance 1010% which is 7x faster than the custom instruction. WHY? Because the whole function is placed in HW, you can collapse both loops and there is where all the performance gain is. But in order to collapse the loops, you have now 8 inputs and 8 outputs which is hard to specify in a custom instruction. The custom instruction sounds nice but doesn't really give you that much gain. The FSL has potential of improving your application with 10x or 100x. Gan Perez Ramas, Javier Basilio wrote: > Hello, > >>-----Mensaje original----- >>De: Gan Bilski [mailto:] >>Enviado el: martes, 14 de diciembre de 2004 20:24 >>Para: >>Asunto: Re: [fpga-cpu] Xilinx vs Altera / Microblaze vs Nios??? >> >> >> >>>>* Nios II and Microblaze are roughly of the same architecture. >>>> >>>> >>>However, Nios II is more customizable and Microblaze cannot handle >>>custom instructions (is this true) >>> >>> >>> >>> >>MicroBlaze can do much more by allowing you to do customer functions >>which is far more powerful than custom instructions. >> >> > > Please, can you explain further what do you want to say with "customer functions"? > > As far as I know, the ways to "expand" Microblaze is either a custom OPB-connected hardware or hardware attached to a superlink FIFO. Is this correct? Although that's valid for most applications I think that the "custom opcodes" is really a powerful function. > Best regards, > > Javier Basilio Pez Ramas > GECOM sensors > INDRA Sistemas, S.A. >To post a message, send it to: >To unsubscribe, send a blank message to: >Yahoo! Groups Links >

At 03:22 AM 12/15/2004, you wrote: >Gan or anyone, > > What types of things, specifically, does Altera do in their tools >that is more intuitive than Xilinx? I use both toolsets and I will say that the Altera tools have a more intuitive feel at the GUI. I can't put my finger on any one thing, but I know I learned my way around their menus and controls much more easily. One thing I think is easier to use is viewing the timing analysis results. You can open a critical path in a chip viewer, the paths will all the logic will be highlighted and you can even see all the individual routing delays on the segments. One area where they both suck is in the help files. All too often when you look up a e.g. the "foobar" selection in a dialog box, it tells you that it allows you to select the foobar option. I bloody well know what a dialog box does, I wanted to know what the foobar option is and why I should care about it!!! > What types of things do Xilinx do that are better than Altera's tools? I think it is easier to control the Xilinx tools if you are trying to optimize your design. The Xilinx floorplanner is a big help and the whole RLOC thing is very good. I don't think Altera has anything remotely like RLOCs. > >MicroBlaze can do much more by allowing you to do customer functions > >which is far more powerful than custom instructions. > > > > > > > What is a 'customer function' and why is it better to be able to do >'customer functions' than extend the instruction set. I believe you can add your own hardware and make it part of the CPU and instruction set. > >There are just to many boards that fits this requirement from many > >different companies. > >Xilinx ML401 board is a nice board which fits all your needs and it also > >using our latest FPGA family Virtex4. > > > > > > > Does the free webpack ISE tool work with this board? That purely depends on the chip on the board. Check on the Xilinx web site to see if the webpack tools support that chip. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX