Yes, VPB Bus works in the same clock (PCLK) as CLK on 2129 / 2292.
On 20 Mar 2007 02:49:34 -0700, Andrew Berney wrote: >
> Hi Bertrik,
>
> certainly the 2292 can run happily at 60MHz with a VPBDIV set to 1
> peripheral clock per main clock cycle. I have one here on the bench so no
> worries for you. We're using the can and serial interfaces on board.
>
> Andy
>
> -----Original Message-----
> From: l... [mailto:
> l... ]On Behalf Of
> b...@sikken.nl
> Sent: 19 March 2007 17:19
> To: l...
> Subject: [lpc2000] Maximum PCLK for LPC2292/LPC2294
>
> Hi,
>
> I'd like to be sure that the PCLK on a LPC2292/LPC2294 can go up to 60
> MHz.
> I expect this to be the case from my experience so far with the LPC2148,
> however the LPC2292/LPC2294 user manual is making me doubt that.
>
> Can anyone clarify the following quote from the user manual:
> "The VPB Divider serves two purposes. The first is to provides peripherals
> with desired pclk via VPB bus so that they can operate at the speed chosen
> for the ARM processor. In order to achieve this, the VPB bus may be slowed
> down to one half or one fourth of the processor clock rate. Because the
> VPB
> bus must work properly at power up (and its timing cannot be altered if it
> does not work since the VPB divider control registers reside on the VPB
> bus), the default condition at reset is for the VPB bus to run at one
> quarter speed."
> (the second purpose described in the UM is reduction of power consumption
> which is of no concern in my application).
>
> To me the quote suggests that some peripherals may not operate without a
> divider, however I cannot find anything about a maximum PCLK for any of
> the built-in peripherals.
>
> Kind regards,
> Bertrik
>
>
>
certainly the 2292 can run happily at 60MHz with a VPBDIV set to 1
peripheral clock per main clock cycle. I have one here on the bench so no
worries for you. We're using the can and serial interfaces on board.
Andy
-----Original Message-----
From: l... [mailto:l...]On Behalf Of
b...@sikken.nl
Sent: 19 March 2007 17:19
To: l...
Subject: [lpc2000] Maximum PCLK for LPC2292/LPC2294
Hi,
I'd like to be sure that the PCLK on a LPC2292/LPC2294 can go up to 60
MHz.
I expect this to be the case from my experience so far with the LPC2148,
however the LPC2292/LPC2294 user manual is making me doubt that.
Can anyone clarify the following quote from the user manual:
"The VPB Divider serves two purposes. The first is to provides peripherals
with desired pclk via VPB bus so that they can operate at the speed chosen
for the ARM processor. In order to achieve this, the VPB bus may be slowed
down to one half or one fourth of the processor clock rate. Because the
VPB
bus must work properly at power up (and its timing cannot be altered if it
does not work since the VPB divider control registers reside on the VPB
bus), the default condition at reset is for the VPB bus to run at one
quarter speed."
(the second purpose described in the UM is reduction of power consumption
which is of no concern in my application).
To me the quote suggests that some peripherals may not operate without a
divider, however I cannot find anything about a maximum PCLK for any of
the built-in peripherals.
Kind regards,
Bertrik
Reply by Karl Olsen●March 19, 20072007-03-19
---- Original Message ----
From:
To:
Sent: Monday, March 19, 2007 6:17 PM
Subject: [lpc2000] Maximum PCLK for LPC2292/LPC2294
> I'd like to be sure that the PCLK on a
LPC2292/LPC2294 can go up to
> 60 MHz. I expect this to be the case from my experience so far with
> the LPC2148, however the LPC2292/LPC2294 user manual is making me
> doubt that.
>
> Can anyone clarify the following quote from the user manual:
> "The VPB Divider serves two purposes. The first is to provides
> peripherals with desired pclk via VPB bus so that they can operate at
> the speed chosen for the ARM processor. In order to achieve this, the
> VPB bus may be slowed down to one half or one fourth of the processor
> clock rate. Because the VPB bus must work properly at power up (and
> its timing cannot be altered if it does not work since the VPB
> divider control registers reside on the VPB bus), the default
> condition at reset is for the VPB bus to run at one quarter speed."
> (the second purpose described in the UM is reduction of power
> consumption which is of no concern in my application).
>
> To me the quote suggests that some peripherals may not operate
> without a divider, however I cannot find anything about a maximum
> PCLK for any of the built-in peripherals.
Reply by "sub...@aeolusdevelopment.com"●March 19, 20072007-03-19
bertrik Wrote >I'd like to be sure that the PCLK on a
LPC2292/LPC2294 can go up to 60 MHz.
>I expect this to be the case from my experience so far with the LPC2148,
>however the LPC2292/LPC2294 user manual is making me doubt that.
>
>Can anyone clarify the following quote from the user manual:
>"The VPB Divider serves two purposes. The first is to provides peripherals
>with desired pclk via VPB bus so that they can operate at the speed chosen
>for the ARM processor. In order to achieve this, the VPB bus may be slowed
>down to one half or one fourth of the processor clock rate. ...
I've seen pretty much the same quote in all the User Manual's
I've read
starting with the 2104/5/6. I've not yet seen a peripheral with a
documented upper rate.
Reply by bert...@sikken.nl●March 19, 20072007-03-19
Hi,
I'd like to be sure that the PCLK on a LPC2292/LPC2294 can go up to 60
MHz.
I expect this to be the case from my experience so far with the LPC2148,
however the LPC2292/LPC2294 user manual is making me doubt that.
Can anyone clarify the following quote from the user manual:
"The VPB Divider serves two purposes. The first is to provides peripherals
with desired pclk via VPB bus so that they can operate at the speed chosen
for the ARM processor. In order to achieve this, the VPB bus may be slowed
down to one half or one fourth of the processor clock rate. Because the VPB
bus must work properly at power up (and its timing cannot be altered if it
does not work since the VPB divider control registers reside on the VPB
bus), the default condition at reset is for the VPB bus to run at one
quarter speed."
(the second purpose described in the UM is reduction of power consumption
which is of no concern in my application).
To me the quote suggests that some peripherals may not operate without a
divider, however I cannot find anything about a maximum PCLK for any of
the built-in peripherals.
