Hi,

This feature is also available on the PowerPC processor
(ie: MPC 860).

This ship has two integrated UPM (user programmable machine)
to handle the signals (and timing) required by the memory
(FPM/EDO/SDRAM). 8 Chip-Select lines are also automaticaly
generated by the processor (16 registers are used to set
the start address and the page size).

When the processor is power-up, CS0 is activated 
(CS0 is usually ROM).

No external chipset = no glue !

Regards
Emmanuel.

Nitin Skandan wrote:
> I have read that Motorola colfire series of processors provides a
> glueless memory interface. What exactly does this term mean.

Nitin Skandan wrote:
> I have read that Motorola colfire series of processors provides a
> glueless memory interface. What exactly does this term mean. I tried
> google search but i could not get a satisfying answer. Please help
> Thank you

It means that you can interface the memory directly, without the 
requirement for interface logic ('glue logic').

Leon

I have read that Motorola colfire series of processors provides a
glueless memory interface. What exactly does this term mean. I tried
google search but i could not get a satisfying answer. Please help
Thank you

NITIN S