Hi,
I'm attempting to use a real-time clock (DS1306) by interfacing it with
a HC08GP32 microcontroller using the SPI. To get my algorithm working, I am
using some of the extra RAM located in the DS1306 to write a few registers
and then attempt to read them. It seems that the writing part works fine;
however, when I attempt to read back what I've written, I get varying
results. I'm using CodeWarrior software for my debugging. When I single
step thru the program, everything works fine (both write and read).
However, when I run the program (no breakpoints, I do not read all the
registers correctly. I do believe that the write part is working...as I can
run this part fullspeed with no problem. However, the read part does not
work full speed. Some of my assembly code is shown here: Any suggestions?
main:
rsp
mov #$01,CONFIG1 ; disable COP watchdog
sei
clra
clrx
clr one ; Clear RAM variables
clr two
mov #$1D,DDRD ; Write enable MOSI,SPSCK,SS $0007
bclr ss,PORTD ; CHPA must be '1'
mov #$08,SPCR
mov #$2A,SPCR ; Enable SPI control register $0010
mov #$02,SPSCR ; Set divisor for baud rate at 128 $0011
bset ss,PORTD ; Activate DS1306 for read/write
mov #$8F,SPDR ; Address of Control Register on DS1306
brclr spte,SPSCR,*
mov #$04,SPDR ; Enable write (bit7), enable 1Hz (bit2)
brclr spte,SPSCR,*
jsr Toggle_SS ; Reset DS1306
mov #$A0,SPDR ; Address of RAM for writing
brclr spte,SPSCR,*
mov #$13,SPDR ; Write to $A0 on DS1306
brclr spte,SPSCR,*
mov #$22,SPDR ;
brclr spte,SPSCR,*
mov #$33,SPDR ;
brclr spte,SPSCR,*
mov #$44,SPDR ;
brclr spte,SPSCR,*
mov #$55,SPDR ;
brclr spte,SPSCR,*
mov #$66,SPDR ;
brclr spte,SPSCR,*
jsr Toggle_SS ; Reset DS1306
lda SPSCR
lda SPDR
mov #$20,SPDR ; Address of RAM for reading
brclr spte,SPSCR,*
jsr DELAY1
mov #$03,SPDR ; Read config register...dummy write
**************Works OK fullspeed until here.
brclr spte,SPSCR,*
jsr DELAY1
mov SPDR,one
mov #$03,SPDR ; Read config register...
brclr spte,SPSCR,*
jsr DELAY1
mov SPDR,two
******************************************************************
Toggle_SS:
bclr ss,PORTD
jsr DELAY1
bset ss,PORTD
lda SPSCR
lda SPDR
rts
******************************************************************