If you want to delay CS, just control CS yourself. Take it out of the set
of pins that SPI controls.

Alan KM6VV Start a New Thread

--- In A..., Caglar Akyuz wrote:
>
> Matthias Wieloch wrote:
> >
> >
> > I already tried and for most of my devices it works. But now I
don't get
> > valid answers from my SPI ADC.
> > Do they tied to same CS? CSAAT is in SPI_CSR register.

I have a decoder connected to the 4 CS lines and I set all 4 SPI_CSR
with the same value.

> > With CSAAT = 1 the NPCS lines keep their state although I change
the PCS
> > field in SPI_MR
> > Seems logical. According to datasheet CS do not rise after the
transfer
> until another transfer is initiated from another CS. In this case
you
> may consider Then you may consider using CS in PIO mode( or maybe
the
> LASTXFER bit if it may help).

I also thought about seting CS maually but why re-inventing the
wheel ;)
LASTXFER did the trick. Just setting this bit at the end of the
transfer seems to take long enough so that the SCK signal is
really "0" when CS lines are risen.
> Excuse me if I don't understand the situation correctly. I just
couldn't
> realized your layout.

But despite the sparse information you showed mie the right way.
Thanks

> Regards
> Caglar Akyuz
> Start a New Thread

Matthias Wieloch wrote:
> I already tried and for most of my devices it works. But now I don’t get
> valid answers from my SPI ADC.
>

Do they tied to same CS? CSAAT is in SPI_CSR register.

> With CSAAT = 1 the NPCS lines keep their state although I change the PCS
> field in SPI_MR
>

Seems logical. According to datasheet CS do not rise after the transfer
until another transfer is initiated from another CS. In this case you
may consider Then you may consider using CS in PIO mode( or maybe the
LASTXFER bit if it may help).

Excuse me if I don't understand the situation correctly. I just couldn't
realized your layout.

Regards
Caglar Akyuz Start a New Thread

I already tried and for most of my devices it works. But now I don't get
valid answers from my SPI ADC.

With CSAAT = 1 the NPCS lines keep their state although I change the PCS
field in SPI_MR

_____

Von:
sentto-14415064-714-1182854542-matthias_wieloch=w...@returns.groups.yahoo.
com
[mailto:sentto-14415064-714-1182854542-matthias_wieloch=w...@returns.group
s.yahoo.com] Im Auftrag von Caglar Akyuz
Gesendet: Dienstag, 26. Juni 2007 12:42
An: A...
Betreff: Re: [AT91SAM] SPI and CSAAT=0

saiberion wrote:
> Hi,
> I have a problem concerning the SPI chip select. The spi is connected
> to a pld.
>
> Due to the logic inside the pld there is a problem after access on spi
> devices with addresses the need PCS3 to be active. After a spi access
> when all CS lines are to be risen it occurs that a shift register
> connected to a address that only differs in PCS3 bit does a shift
> because SCK is still high while not all address lines are risen.
>
> Is there a way to have some delay after last SCK until the SPI
> deallocates CS lines?
>

doesn't using CSAAT help? Start a New Thread

saiberion wrote:
> Hi,
> I have a problem concerning the SPI chip select. The spi is connected
> to a pld.
>
> Due to the logic inside the pld there is a problem after access on spi
> devices with addresses the need PCS3 to be active. After a spi access
> when all CS lines are to be risen it occurs that a shift register
> connected to a address that only differs in PCS3 bit does a shift
> because SCK is still high while not all address lines are risen.
>
> Is there a way to have some delay after last SCK until the SPI
> deallocates CS lines?
>

doesn't using CSAAT help? Start a New Thread

> Is there a way to have some delay after last SCK until the SPI
> deallocates CS lines?

Bring the CS lines into the PLD.
Use their falling edges to clock a D-FF. Cascade to another D-FF, clocked by the
last falling/rising SCK edge.
This output should provide enough delay. If not, run it through a couple more latches
clocked by opposite polarities of a suitable G clock.

Best Regards,
Kris

________________________________________
From: A... [mailto:A...] On Behalf Of saiberion
Sent: Tuesday, 26 June 2007 5:22 PM
To: A...
Subject: [AT91SAM] SPI and CSAAT=0

Hi,
I have a problem concerning the SPI chip select. The spi is connected
to a pld.

Due to the logic inside the pld there is a problem after access on spi
devices with addresses the need PCS3 to be active. After a spi access
when all CS lines are to be risen it occurs that a shift register
connected to a address that only differs in PCS3 bit does a shift
because SCK is still high while not all address lines are risen.

Is there a way to have some delay after last SCK until the SPI
deallocates CS lines? Start a New Thread

Hi,
I have a problem concerning the SPI chip select. The spi is connected
to a pld.

Due to the logic inside the pld there is a problem after access on spi
devices with addresses the need PCS3 to be active. After a spi access
when all CS lines are to be risen it occurs that a shift register
connected to a address that only differs in PCS3 bit does a shift
because SCK is still high while not all address lines are risen.

Is there a way to have some delay after last SCK until the SPI
deallocates CS lines? Start a New Thread