In article <420d1f5f$1@clear.net.nz>,
Jim Granville <no.spam@designtools.co.nz> wrote:
[...]
>Good software for 22V10 code is Atmel's free WinCUPL.
IMO: ICT's place is better.
--
--
kensmith@rahul.net forging knowledge
Reply by Fred Bloggs●February 12, 20052005-02-12
Glenn Gundlach wrote:
> Well sir, I beg to differ a little. My TV remote transcoder boards are
> in transit from Advanced Circuits. It uses a 68HC908JK3 to listen to
> the IR receiver. I needed a 38kHz for pulsing the IR transmit LED. With
> the 32MHz osc, thats divide by 840 so I have an 'F163 to prescale by 15
> to
> 2.133MHz and then do the rest of the counting and gating in a 22V10
> (38095 Hz is close enough). It divides by 56 with a 50/50 duty cycle by
> counting from 4 to 60 in the 6 bit counter and then the IRQ to the
> controller and the gating with the transmit, also from the controller.
> The 22V10 is just dandy for this in spite of being a power hog. I can
> live with it. Using MSI counters would have been more tedious to work
> out and would have used more packages. Gating changes in a GAL are
> easily reprogrammed.
> GG
>
That sounds like a situation where the PAL makes sense- because you have
other logic in addition to plain counting, but in general, it's a waste
of money to use a PAL to perform a generic MSI function- like a 10-bit
register or a 4-bit counter. Lessee- 56= 7 x 8 so that's a DIV 7 into a
free-running 3-bit binary counter. This would not be bad in SOT:
View in a fixed-width font such as Courier.
,----------------------------------+
| 74HCT393 1/4 |
CLK | ----------- 74HCT00 |
| |____ | |
2.133MHz>-+---|-----|1CLK 1Q0| |
| | | | __ |
| | ,--|1CLR 1Q1|---------| \ |
| | | | | | o--'
| | | | 1Q2|-----+---|__/
| | | | | |
| | | | 1Q3| |
| | | | | | CLK
| | | | | +---+-> ---
| | | | | | 7
| | | | | |
| | | |____ | |
| '-----|2CLK 2Q0|----. |
| | | | | |
'---------|2CLR 2Q1| | |
| | | | |
| | 2Q2| | |
| | | | |
| | 2Q3| | |
| ----------- | |
| | |
'-------------------' |
|
+-------------------------+
|
| 74HCT393
| -----------
| |____ |
+---|1CLK 1Q0|
| |
'0'-+-|1CLR 1Q1|
| | | CLK
| | 1Q2|---------> --- duty 50/50
| | | 56
| | 1Q3|
| | |
| | |
| | |
| | |
| |____ |
+-|2CLK 2Q0|
| | |
+-|2CLR 2Q1|
| |
| 2Q2|
| |
| 2Q3|
-----------
Reply by Glenn Gundlach●February 12, 20052005-02-12
Well sir, I beg to differ a little. My TV remote transcoder boards are
in transit from Advanced Circuits. It uses a 68HC908JK3 to listen to
the IR receiver. I needed a 38kHz for pulsing the IR transmit LED. With
the 32MHz osc, thats divide by 840 so I have an 'F163 to prescale by 15
to
2.133MHz and then do the rest of the counting and gating in a 22V10
(38095 Hz is close enough). It divides by 56 with a 50/50 duty cycle by
counting from 4 to 60 in the 6 bit counter and then the IRQ to the
controller and the gating with the transmit, also from the controller.
The 22V10 is just dandy for this in spite of being a power hog. I can
live with it. Using MSI counters would have been more tedious to work
out and would have used more packages. Gating changes in a GAL are
easily reprogrammed.
GG
Reply by Fred Bloggs●February 12, 20052005-02-12
>
> I have a 6.144Mhz crystal and I am trying to
> generate the 9600*16 ~ 154k clock needed by the
> 8251 UART and the ~ 1Mhz system clock.
>
> I dont want to use the 74ls* series ripple
> counters and I have a bunch of 22v10 PAL chips
> lying around.
>
> I have been thinking about how best to do this,
> using what I have.
>
> Basically I need to divide the 6.144Mhz by 40.
> First by 5 to realize the system clock, then by
> 8 to realize the UART baud clock.
>
> With the 22v10 I could set aside two 3 bit
> "registered" outputs for a GLITCH FREE
> synchronous counter ... But I would need the
> output of one to drive the other ... and I
> dont see how I can do this when they all
> share a common CLK input.
>
> By the way I also have a bunch of 74ls112 dual
> J/K flip flops lying around (about 25). I
> thought I might use that along with the 22v10'
> to realize my clock divider.
The 22V10 is not appropriate for a simple task like this one- the job
can be done for about $0.70 (qty 1 ea.) with more readily available and
better performing MSI logic in a 14-pin IC like shown below. The
74HCT393 is a dual 4-bit ripple counter arranged so that 1CTR cycles
through states 0->4. The transition into state 5 is transient in that
the NAND decodes Q0,Q2 hazard free to apply a negative transition to
/2CLK which advances from state 0->1 so that 2Q0 clears 1CTR- then the
CLK clears 2CTR during its HIGH state removing the 1CLR through 2Q0 well
in advance of the next CLK H->L transition on /1CLK for a repeat of the
sequence. The 1Q1 is a solid 40/60 duty CLK/5 output. Then you can apply
the CLK/5 to *any* 4-bit binary counter allowed to free run to obtain
/2, /4, /8, /16 from the respective Q0, Q1, Q2, Q3 outputs- and at
perfect 50/50 duty. It is important you use the HCT393 and HCT00 to meet
the various requirements of things like hazard free NAND state decode,
minimum CLK pulse width, reset recovery and a few other more or less
subtle timing considerations that make asynchronous reliable. If you
don't have any spare NANDs then use the other three gates to square up
that CLK input and buffer CLK/5 output.
View in a fixed-width font such as Courier.
,----------------------------------+
| 74HCT393 1/4 |
CLK | ----------- 74HCT00 |
| |____ | __ |
6.144MHz>-+---|-----|1CLK 1Q0|---------| \ |
| | | | | o--'
| | ,--|1CLR 1Q1|--. ,--|__/
| | | | | | |
| | | | 1Q2|------'
| | | | | | CLK
| | | | 1Q3| '--------> --- duty:
| | | | | 5 40/60
| | | | |
| | | | |
| | | | |
| | | |____ |
| '-----|2CLK 2Q0|----.
| | | | |
'---------|2CLR 2Q1| |
| | | |
| | 2Q2| |
| | | |
| | 2Q3| |
| ----------- |
| |
'-------------------'
Reply by Ken Smith●February 11, 20052005-02-11
In article <0m5q01t63g4fmadvvtfu79aeu71plhfm1q@4ax.com>,
John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
>On Fri, 11 Feb 2005 19:33:52 +0000 (UTC), kensmith@green.rahul.net
>(Ken Smith) wrote:
>
>>In article <pssp01940r9trdauq7epc8l4fsee71c8ti@4ax.com>,
>>John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
>>[...]
>>>Clock all the flops at the same rate (you have to, anyhow) and decode
>>>a single state of the faster counter and use that as a clock enable on
>>>the slower counter, effectively a "carry in."
>>
>>I think John meant this but it isn't clear so:
>>
>>If you make the decoded output from the fast section registered. you get
>>the combined logic without adding a lot of delay.
>>
>
>Actually, no; it can just be a static decode of one fast counter state
>that enables the slower counter. It's no different from any other
>carry. If you have a pin to spare, the carry state can be explicitly
>decoded and then used in the counter below; if not, you have to
>include all the decode terms in every flop of the lower counter, which
>is a nuisance.
Yes, at low speeds this works, such as the 6MHz that is the case here.
At higher speeds, the second layer of logic can become a source of
troubles.
>Counters *are* a pain in a 22V10; there's no XOR available, so as the
>counters get longer the number of logic terms explodes. It's tedious
>to do by hand.
Yes, thats why God made the copy and paste operations. Each equation
builds up from the previous. For longer counters a psudo-random
generator using a shift register and one XOR can often save you a lot of
terms. This can be the way to go if you are trying to divide by something
like 245.
--
--
kensmith@rahul.net forging knowledge
Reply by mike●February 11, 20052005-02-11
sam wrote:
> Hello all:
>
>
> I have a 6.144Mhz crystal and I am trying to
> generate the 9600*16 ~ 154k clock needed by the
> 8251 UART and the ~ 1Mhz system clock.
>
> I dont want to use the 74ls* series ripple
> counters and I have a bunch of 22v10 PAL chips
> lying around.
>
> I have been thinking about how best to do this,
> using what I have.
>
> Basically I need to divide the 6.144Mhz by 40.
> First by 5 to realize the system clock, then by
> 8 to realize the UART baud clock.
>
> With the 22v10 I could set aside two 3 bit
> "registered" outputs for a GLITCH FREE
> synchronous counter ... But I would need the
> output of one to drive the other ... and I
> dont see how I can do this when they all
> share a common CLK input.
>
> By the way I also have a bunch of 74ls112 dual
> J/K flip flops lying around (about 25). I
> thought I might use that along with the 22v10'
> to realize my clock divider.
>
> Any ideas?
>
I guess these come in all kinds of versions, so depends on which
you have.
Check out the power consumption before you go too far.
I've been using old GAL20V8s cause I have a lifetime supply. But the
high current drain makes 'em unsuitable for battery operated systems.
Silly things consume 17mA just sitting idle. Lots more when you clock 'em.
mike
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Reply by sam●February 11, 20052005-02-11
On Fri, 11 Feb 2005 10:06:21 -0800, John Larkin wrote:
> Clock all the flops at the same rate (you have to, anyhow) and decode
> a single state of the faster counter and use that as a clock enable on
> the slower counter, effectively a "carry in."
Thanks John.
So basically I would setup 3 Dflop outputs to
count through
0 - 2 - 6 - 4 - 5 - 7 - 3 -1 glitch free
(I have been working with PAL's for only a few
months CANT you tell ;))
then use 7 (decoded) to do two things
1) toggle one JK flip flop in the 74ls112
this gets fed as my system clock
2) enable the second clock (use reserved pin
"Clk2Enable")
the second can count through
0 - 2 - 6 - 4 - 5
then use 5 (decoded) to
1) clear "Clk2Enable"
2) toggle second JK flip flop in the 74ls112
this gets fed to my 8251 UART's baud clk pin.
Is that what you mean?
Thanks to all for the help and suggestions.
I am trying to realize my dream ... designing
a game machine.
I thought I'd start by designing a 6504 sbc
from scratch ... I am almost done ... its just
at the last minute I thought to use the same
crystal ... and divide down to get the clock
I want for the processor and the uart
there goes the Keep It Simple S..... principle!
Reply by CBFalconer●February 11, 20052005-02-11
John Larkin wrote:
>
... snip ...
>
> Counters *are* a pain in a 22V10; there's no XOR available, so as
> the counters get longer the number of logic terms explodes. It's
> tedious to do by hand.
Consider shift registers with a feedback function. For example,
shifting left with the feedback being the complement of the high
order bit, you get the sequence:
000
001
011
111
110
100
000 -> i.e. a scale of 6.
You can build anything you like with a suitable feedback. Take the
nor of the middle and left bits and:
000
001
011
110
100
000 -> i.e. a scale of 5.
Always check what the unused codes will do. For the scale of 5
010 -> 100 ok, main sequence
101 -> 010 ok, because of above
110 -> 100 ok, main sequence.
but for the scale of 6:
010 -> 101 -> 010 so precautions need be taken. Elaborating the
feedback will usually do it.
--
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Reply by Meindert Sprang●February 11, 20052005-02-11
"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:1gbq015ibg617j0nrmnj227cllfkphlj5j@4ax.com...
> Yeah, that's a lot easier than APEEL, where you have to grind out the
> product terms.
>
>
> " NOW DO THE COUNTER BITS...
>
> MA1 = /MA1 * /MAX
>
> MA2 = /MA2 * MA1 * /MAX
> + MA2 * /MA1 * /MAX
>
> MA3 = /MA3 * MA2 * MA1 * /MAX
> + MA3 * /MA2 * /MAX
> + MA3 * /MA1 * /MAX
<snip>
Ha, and exactly that could be distilled from the output of TangoPLD
>
> So in a 22V10 the product terms get burned up fast as the counter gets
> longer, no matter how you compile it.
Correct, however my example *was* made for a 22V10. And it worked (8 bits
wide).
Meindert
Reply by Bob Stephens●February 11, 20052005-02-11
On Fri, 11 Feb 2005 12:40:41 -0800, John Larkin wrote:
> Counters *are* a pain in a 22V10; there's no XOR available, so as the
> counters get longer the number of logic terms explodes. It's tedious
> to do by hand.
>
> John
I found an *OLD* one of mine compiled with AMD's 'PLPL' logic compiler -
which used to be free - and did give you an XOR operator - (%);
Made counters pretty easy.
Bob
DEVICE ad2b (p22v10)
" same as Redcor ad2.pld except master reset "
PIN
" Generates address bits 0 - 6 "
"---- Output Pin Assignments ----"
compare1 = 18 (output active_low combinatorial)
compare2 = 19 (output active_low combinatorial)
latch = 17 (output active_high combinatorial)
a[6] = 14 (output active_high registered)
a[5] = 15 (output active_high registered)
a[4] = 16 (output active_high registered)
a[3] = 20 (output active_high registered)
a[2] = 21 (output active_high registered)
a[1] = 22 (output active_high registered)
a[0] = 23 (output active_high registered)
busy2=1 (clk_input) "add_ctr_adv "
d[6] = 2 (input combinatorial)
d[5] = 3 (input combinatorial)
d[4] = 4 (input combinatorial)
d[3] = 5 (input combinatorial)
d[2] = 6 (input combinatorial)
d[1] = 7 (input combinatorial)
d[0] = 8 (input combinatorial)
master = 9 (input combinatorial)
busy = 11 (input combinatorial) ;
"Logic Equation Section"
BEGIN
enable(a[0:6]) = #b1111111;
enable(compare1,compare2,latch)= #b111;
reset(a[0:6]) = /master; "reset to 0"
a[0]=/a[0];
a[1]=a[1]%a[0];
a[2]=a[2]%(a[1]*a[0]);
a[3]=a[3]%(a[2]*a[1]*a[0]);
a[4]=a[4]%(a[3]*a[2]*a[1]*a[0]);
a[5]=a[5]%(a[4]*a[3]*a[2]*a[1]*a[0]);
a[6]=a[6]%(a[5]*a[4]*a[3]*a[2]*a[1]*a[0]);
compare1=(a[0]%d[0])*(a[1]%d[1])*(a[2]%d[2])*(a[3]%d[3]);
compare2=(a[4]%d[4])*(a[5]%d[5])*(a[6]%d[6]);
latch=/compare1*/compare2*/busy;
END.