Spotted this in comp.arch.transputer and in comp.arch.fpga by johnjakson JJ dated 02/04/2005 (yes 2nd of April) Announcement This first partial release date was chosen to be April 1st, to suggest some light hearted foolery here and to force myself to get something out to show for a couple years of work. Indeed the joke is really on all of us for making do with so much less than might have been possible with todays 90nm processes and 40yrs of "Computer Science", its been a very long time since good design made more sense. And for all the Windows PCs that still take 2mins to boot, and then get attacked as soon as they connect, and never really quite work right. And for all the Windows spambots (theres probably more of these than Inmos Transputers made). And for all the x86s that keep our homes warmer than necessary. And for all the Transputer domains out there "still being developed". And for all the Inmos's, HPs, DECs, SGIs, NeXTs, Be's that go down the hole. The development release will consist of 5 packages starting today with the initial document bundle & the R16_ISA simulator all "AS IS" to be later followed by the R16_RTL, R16_VLG. & R16_Vpp packages. Since there is as yet no web site (transputer.com & others are too busy selling links), I am releasing this through email as a 100k zipped file that should run most anywhere. None of the packages have been tested outside VC6.0 on W2K but they really are just hello_world type apps. The project started under BeOS but the FPGA tools don't go there. Depending on how this goes, I will look for interested web partners to host this material after more editing. The license will be either BSD/MIT if I decide to release completely free, or GPL/$opt-out if things look good. To receive the initial package please fill out the form and send to address below. Name: Affiliation: City Location: Tel: Email: Web links: Reason for interest: Join interest, Yes,No,Maybe: Very brief bio of work done in Transputers, Occam, FPGAs, parallel computing, compilers or whatever is relevant. I am particularly interested to hear from a variety of potential users, architects, implementors, HW or SW, Compiler, and OS people, VC-investors perhaps, webmasters, authors doc writers and even ex Inmos folks etc. Corrections and feedback most welcome. Hope this is of some interest to the Transputer community regards johnjakson at usa dot com (ignore yahoo, thats for the spam) or just 508 480 0777 from 9 to 9 to chat Marlboro Mass "Just 10 mins from past DEC sites in most directions, the old Mill, the Alpha center!" Okay so the 1st request goes to Antti from the FPGA NG. I will be bunching send outs in 10s or so till I see how it plays out and consider web hosting and other development offers as they come in. I will check in every so often so some request may take hours. Although I am not releasing any of the synthesizeable Verilog, the schematics in ascii gives quite a bit of detail away that is not even described by the included ISA model but that would leave any would be cloners atleast 6months behind, and besides there is quite a bit of stuff to do in the ISA model to migrate over to C cycle model and then the Verilog.code such as most of the Process features. The important thing right now is to air the current architecture warts and all and see if it has any holes in it that could sink it. regards all johnjakson at usa dot com Transputer delivery comp.arch.fpga,comp.arch,comp.dsp If anyone is still interested in Transputers, I am now releasing the 1st half of a new FPGA Transputer through email, mostly docs but also an Instruction Set simulator, the C cycle model and Verilog sources for later, all works in progress better than spam I presume see comp.sys.transputer regards all johnjakson at usa dot com