Reply by microbit May 25, 20062006-05-25
At 16 bits of AD conversion you must take extreme care that ANY noise stays
out of your
Vref (happy trails with internal Vref), your analog input and grounding.
Sampling & hold must match the time constant well.

As example, 3 Volts span / 16 bit or 2^16 = 3 / 65536 = 45.77 uV for ONE bit
change.
A mere 1 mV of noise =~ 22 steps of 1 bit......

-- Kris

>-----Original Message-----
>From: msp430@msp4... [mailto:msp430@msp4...] On Behalf Of Resul BEDEL
>Sent: Thursday, 25 May 2006 4:02 PM
>To: msp430@msp4...
>Subject: [msp430] ADC of F2013. Is it really 16 bit?
>
>Hi everyone,
>  I am newbie in MSP430 series microcontrollers, and I started from latest
one which is
F2013. I
>am working on application which based on analog
inputs, 16 bit Sigma Delta ADC of F2013
was
>nice choice, I thought...
>  But when I design my prototype circuit and read the signal the result was
not so cool.
>  At 1MHz CPU frequency, 1024 OSR, 1.st clock divider=8, 2.nd clock
dividerH, CPU uses
internal
>DCO, internal Vref ... I get result in SD16MEM0
which unstable and varies for 4 points
over 65535
>(2 bits).
>
>  And for OSR2, 1.st clock divider =1, 2.nd clock divider=1 (other settings
same as
above) for
>this settings result in SD16MEM0 also unstable and
varies for 16-20 over 65535 (4-5
bits).
>
>  So readings is not 16, but exactly 12-14 bits.Does anybody knows what is
the reason and
what is
>wrong in my settings or hardware.
>
>  Circuit of analog part is attached as jpeg.
>  Best regards...
>
>Send instant messages to your online friends http://uk.messenger.yahoo.com
>
>
>
>
>
>
>.
>
>
>Yahoo! Groups Links
>
>
>
>
>



Beginning Microcontrollers with the MSP430

Reply by Resul BEDEL May 25, 20062006-05-25
Hi everyone,
  I am newbie in MSP430 series microcontrollers, and I started from latest one
which is F2013. I am working on application which based on analog inputs, 16 bit
Sigma Delta ADC of F2013 was nice choice, I thought...
  But when I design my prototype circuit and read the signal the result was not
so cool. 
  At 1MHz CPU frequency, 1024 OSR, 1.st clock divider=8, 2.nd clock dividerH,
CPU uses internal DCO, internal Vref ... I get result in SD16MEM0 which unstable
and varies for 4 points over 65535 (2 bits).
   
  And for OSR2, 1.st clock divider =1, 2.nd clock divider=1 (other settings same
as above) for this settings result in SD16MEM0 also unstable and varies for
16-20 over 65535 (4-5 bits).
   
  So readings is not 16, but exactly 12-14 bits.Does anybody knows what is the
reason and what is wrong in my settings or hardware.
   
  Circuit of analog part is attached as jpeg.
  Best regards...

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