Reply by habib bouaziz-viallet●March 17, 20052005-03-17
Le Wed, 16 Mar 2005 20:33:01 +0100, Volker Bosch a �crit�:
> Hello Habib,
>
> habib bouaziz-viallet <habib@mynewserverposfix.com> wrote:
>
>> I'm quite puzzled. SPI may be reloaded by AVR as Slave device regardless
>> ~SS level ?
>
> Yes. But you have to write the first data byte into the transmit register
> `by hand' before you enable the SPI interface. When /SS is pulled low, the
> data byte in the transmit register is shifted out (Beware: no SPI
> interrupt is triggered when /SS is pulled low!). When the last bit of the 1st
> byte is shifted out, the first SPI interrupt is executed by the MCU. The
> irpt-handler has to read the 1st received byte from the receive register
> and write the 2nd byte to be transmitted into the transmit register.
Hi Volker !
Many many thanks for your blessed relief !
SPI comm between AVR and MSM7705 CoDec now works with AVR as a slave. You
're right for timming shift reg updating (1/2 MCU clock phase)
Thankx, Habib
betula.fr
> I'm quite puzzled. SPI may be reloaded by AVR as Slave device regardless
> ~SS level ?
Yes. But you have to write the first data byte into the transmit register
`by hand' before you enable the SPI interface. When /SS is pulled low, the
data byte in the transmit register is shifted out (Beware: no SPI
interrupt is triggered when /SS is pulled low!). When the last bit of the 1st
byte is shifted out, the first SPI interrupt is executed by the MCU. The
irpt-handler has to read the 1st received byte from the receive register
and write the 2nd byte to be transmitted into the transmit register.
--
****----*-------*-------*-------*-------*-------*-------*-------*----****
*\ Viele -- Volker Bosch \***
**\ Gruesse aus -- E-Mail: vsbosch@z.zgs.de \**
***\ Stuttgart -- http://www.s-line.de/homepages/bosch \*
Reply by habib bouaziz-viallet●March 16, 20052005-03-16
Le Tue, 15 Mar 2005 19:45:56 +0100, Volker Bosch a �crit�:
> habib bouaziz-viallet <habib@mynewserverposfix.com> wrote:
>
> [...]
>> AVR is configured as a slave. SS is grounded, therefore AVR is not able to
>> update SPI shift reg for transmit after a byte is completely received
>> from CodeC. That's why i'm seeking about Master SPI mode with AVR.
>
> Hello Habib,
>
> I use the Mega16 as a slave on an SPI line. And there is no problem to
> transmit more than 8 bit when /SS stays pemanently low. When the 8th
> bit is transmitted, MCU will receive a SPI interrupt (if this interrupt
> is enabled), no matter what logic state /SS has. The only problem is
> that you have only about half a SPI-clock cycle of time for writing the
> next transmit data byte into the transmitter register.
>
> Hope that helps.
Hi Volker,
I'm quite puzzled. SPI may be reloaded by AVR as Slave device regardless
~SS level ?
here a code snippet i tried :
#include <io.h>
#include <interrupt.h>
#include <signal.h>
#include <pgmspace.h>
#include "init.h"
#include "types.h"
#include "uart.h"
#include "maya.h"
#include "pcm.h"
u08 pcm_in[256];
u08 pcm_out[256];
u08 spi_release = 0;
/************************
* SPI Interrupt handler
************************/
SIGNAL (SIG_SPI)
{
static u08 i = 0;
/* Read before Write SPDR !!! */
pcm_out[i] = SPDR;
SPDR = pcm_in[i++];
if (i == 254)
spi_release = 1;
if (i == 255)
i = 0;
}
AVR as a slave, SPDR never been updated in that code. In fact, the same
byte received by the slave (MOSI) is transmitted the next shift process
into MISO pin.
Habib
betula.fr
> AVR is configured as a slave. SS is grounded, therefore AVR is not able to
> update SPI shift reg for transmit after a byte is completely received
> from CodeC. That's why i'm seeking about Master SPI mode with AVR.
Hello Habib,
I use the Mega16 as a slave on an SPI line. And there is no problem to
transmit more than 8 bit when /SS stays pemanently low. When the 8th
bit is transmitted, MCU will receive a SPI interrupt (if this interrupt
is enabled), no matter what logic state /SS has. The only problem is
that you have only about half a SPI-clock cycle of time for writing the
next transmit data byte into the transmitter register.
Hope that helps.
--
****----*-------*-------*-------*-------*-------*-------*-------*----****
*\ Viele -- Volker Bosch \***
**\ Gruesse aus -- E-Mail: vsbosch@z.zgs.de \**
***\ Stuttgart -- http://www.s-line.de/homepages/bosch \*
Reply by Meindert Sprang●March 15, 20052005-03-15
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
news:pan.2005.03.15.09.25.11.617358@mynewserverposfix.com...
> SS controlled by soft, AVR as a Master ... it could work, but i will try
> to find out more about AVR Slave mode. In fact i'm not very inclined for
> the moment to cut PCB traces and so ... for implement AVR Master mode.
Mmm, you would have to cut SS anyway if you want to run the AVR in slave
mode, to be able to read and write to the SPI shift register.
Meindert
Reply by habib bouaziz-viallet●March 15, 20052005-03-15
Le Tue, 15 Mar 2005 10:11:06 +0100, Meindert Sprang a �crit�:
> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
> news:pan.2005.03.15.09.00.34.946375@mynewserverposfix.com...
>> > So your problem is SS stays low,
>> Rrrrrriiiiiiiight !
>> you cannot access the shift register. Can't
>> > you connect SS to the same sync signal that you feed to RSYNC?
>> I cannot do that regarding FSYNC waveform. It seems that a little more
>> complex signals generation circuitry must be implemented to drive SS
>> properly.
>
> But if you would run the AVR as master and use the SS pin to drive RSYNC, it
> would work, right?
> The level on the SS pin must be controlled by your software anyway, so you
> can time it as you please.
SS controlled by soft, AVR as a Master ... it could work, but i will try
to find out more about AVR Slave mode. In fact i'm not very inclined for
the moment to cut PCB traces and so ... for implement AVR Master mode.
For sure anyway it will work this very day.
thanx, Habib
betula.fr
Reply by Meindert Sprang●March 15, 20052005-03-15
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
news:pan.2005.03.15.09.00.34.946375@mynewserverposfix.com...
> > So your problem is SS stays low,
> Rrrrrriiiiiiiight !
> you cannot access the shift register. Can't
> > you connect SS to the same sync signal that you feed to RSYNC?
> I cannot do that regarding FSYNC waveform. It seems that a little more
> complex signals generation circuitry must be implemented to drive SS
> properly.
But if you would run the AVR as master and use the SS pin to drive RSYNC, it
would work, right?
The level on the SS pin must be controlled by your software anyway, so you
can time it as you please.
Meindert
Reply by habib bouaziz-viallet●March 15, 20052005-03-15
Le Tue, 15 Mar 2005 09:42:52 +0100, Meindert Sprang a �crit�:
> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
> news:pan.2005.03.15.08.09.18.196326@mynewserverposfix.com...
>> Hi Meindert,
>>
>> Take a look at this :
>> http://cjoint.com/?dpjsxvXDQV
>> AVR is configured as a slave. SS is grounded, therefore AVR is not able to
>> update SPI shift reg for transmit after a byte is completely received
>> from CodeC. That's why i'm seeking about Master SPI mode with AVR.
>
> So your problem is SS stays low,
Rrrrrriiiiiiiight !
you cannot access the shift register. Can't
> you connect SS to the same sync signal that you feed to RSYNC?
I cannot do that regarding FSYNC waveform. It seems that a little more
complex signals generation circuitry must be implemented to drive SS
properly.
Many thanks, Habib
betula.fr
Reply by Meindert Sprang●March 15, 20052005-03-15
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
news:pan.2005.03.15.08.09.18.196326@mynewserverposfix.com...
> Hi Meindert,
>
> Take a look at this :
> http://cjoint.com/?dpjsxvXDQV
> AVR is configured as a slave. SS is grounded, therefore AVR is not able to
> update SPI shift reg for transmit after a byte is completely received
> from CodeC. That's why i'm seeking about Master SPI mode with AVR.
So your problem is SS stays low, you cannot access the shift register. Can't
you connect SS to the same sync signal that you feed to RSYNC?
Meindert
Reply by habib bouaziz-viallet●March 15, 20052005-03-15
Le Mon, 14 Mar 2005 20:21:22 +0100, Meindert Sprang a �crit�:
> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message
> news:pan.2005.03.14.18.45.45.766538@mynewserverposfix.com...
>> Configuring SPI bus in slave mode may require one more signal to drive SS.
>> AVR received and send at the same time DOUT and DIN to and from CoDeC.
>> Master SPI does not require SS driven, IHMO Master mode should be more
>> simple if fortunenately SCK would be a real clock input.
>
> But, by being master, the SPI interface knows exactly when a byte starts,
> because the transmission is started when a byte is written in the data
> register. In slave mode, you only know the beginning of a byte by detecting
> the assertion of SS. In short: what you want is impossible.
>
> Meindert
Hi Meindert,
Take a look at this :
http://cjoint.com/?dpjsxvXDQV
AVR is configured as a slave. SS is grounded, therefore AVR is not able to
update SPI shift reg for transmit after a byte is completely received
from CodeC. That's why i'm seeking about Master SPI mode with AVR.
Believe me i'm not a flasher !
Habib
betula.fr