Our SCR's work well in providing protection, however, the drawback is that
if they are triggered by a high voltage on the pin (around 6V), then the pin is
clamped to ground until the power is removed from the device. This can cause
additional current draw if the pin is being driven externally. To prevent this,
they could put shottky clamping diodes externally on the pins. On future
versions they are supposed to go back to a diode clamp on the I/O, however, most
of the devices available now have the SCR.
Best Regards,
Jim Earle
Senior Field applications Engineer - TSC Microcontrollers
NXP Semiconductors (formerly Philips Semiconductors)
Dallas, TX
----- Original Message -----
From: ksdoubleshooter
To: l...
Sent: Wednesday, September 26, 2007 1:23 AM
Subject: [lpc2000] Re: LPC2366 5V Tolerant pins
Yes, the 5 volt tolerant I/O on the LPC2000 part is more complex. I
have observed an I/O pin that was pulled up to 5 volts measure 5
volts when programmed as an input, but drop to 3.6v when programmed
to an output. This would indicate that the output driver
is "disconnected" from the pin when the pin is an input. They
probably use a bilateral switch, but even this has parasitic diodes
to the supply rails, unless some kind of magic is used.
Ever wonder how the ICL7660 or a MAX232 works to create the negative
voltage with all the parasitic diodes in a CMOS circuit??? Magic.
Jeff
--- In l..., "Danish Ali" wrote:
>
> There's a further complication: most of the "5V tolerant as input"
> pins can also be used as digital outputs.
>
> A digital output normally has a PMOS transistor between Vdd3.3
> and the pin. When Vdd3.3 is not powered, this transistor will also
conduct.
>
> I'm not sure how the structure is changed for a 5V-tolerant pin.
> But this is one reason why the fully-I2C-compatible pins are
> open-drain - they do not have the PMOS transistor and so they
> _are_ 5V-tolerant even when the processor is not powered
> (part of the I2C spec is that a non-powered device should not
> crowbar the signal lines).
>
> Regards,
> Danish
> --- In l..., "ksdoubleshooter" wrote:
> >
> > There is a lot of misinformation going on in this thread. I've
been
> > involved in the design of 3 custom CMOS ASIC's and I know CMOS
> > processes.
> >
> > The clamp diodes on CMOS inputs are optional, however they are
> > almost universally used to protect the gate oxide. A P-well
process
> > was used on the ASIC's that I was involved with. The clamp diode
to
> > ground was fabricated with an N+ diffusion inside of a P-well
with
> > the well tied to ground. The clamp diode to Vdd was a P+
diffusion
> > into the N- substrate. This P+ diffusion was long, skinny and
folded
> > so that it provided series resistance and a clamp to Vdd.
> >
> > Someone in the thread referred to these diodes as body diodes.
That
> > is not correct. Body diodes are the parasitic diodes that are
formed
> > between drain/substrate and source/substrate connnections.
> >
> > Someone also referred to the potential to overheat the input
clamp
> > diodes with too much current. This will not happen -- something
much
> > worse will happen. All CMOS processes that I am aware of have a
> > parasitic thyristor. Triggering this thyristor into conduction is
> > the dreaded "latch up condition" This thyristor is triggered by
too
> > much current into either of the input clamp diodes.
> >
> > 5 volt tolerant inputs are usually fabricated with an n-channel
> > device, where the gate and source are tied to ground and the
drain
> > is tied to the input through some series resistance. The break
down
> > of the body diode provides the clamping at some voltage above 5
> > volts.
> >
> > Jeff
>
--- In l..., "ksdoubleshooter" wrote: >
> Yes, the 5 volt tolerant I/O on the LPC2000 part is more complex. I
> have observed an I/O pin that was pulled up to 5 volts measure 5
> volts when programmed as an input, but drop to 3.6v when programmed
> to an output. This would indicate that the output driver
> is "disconnected" from the pin when the pin is an input. They
> probably use a bilateral switch, but even this has parasitic diodes
> to the supply rails, unless some kind of magic is used.
>
> Ever wonder how the ICL7660 or a MAX232 works to create the negative
> voltage with all the parasitic diodes in a CMOS circuit??? Magic.
>
> Jeff
I was wandering around looking for a low dropout regulator when I ran
across the LP38692 from National Semi. This might be the answer to
guaranteeing that 3.3V is present before 5V is applied because it has
an enable pin controlling the output.
The voltage requirement of the Ven pin is ugly - it basically needs to
be derived from the regulator input voltage. Maybe a transistor
between the uC and Ven.
Richard
Richard
Reply by jsm09a●September 26, 20072007-09-26
> Regardless of how they clamp, the voltage continues
into the core at a
> high level. The more series diodes, the higher that voltage can get.
Sorry, I don't follow "voltage continues into the core". Assuming
that the port was configured as an input, my understanding would be
that extremely little input current would "continue into the core".
On the data sheet, under Static Characteristics, pull-up current (Ipu)
is shown
as zero microamps when the port input voltage is anywhere from 3.3V to 5V.
Reply by ksdoubleshooter●September 26, 20072007-09-26
Yes, the 5 volt tolerant I/O on the LPC2000 part is more complex. I
have observed an I/O pin that was pulled up to 5 volts measure 5
volts when programmed as an input, but drop to 3.6v when programmed
to an output. This would indicate that the output driver
is "disconnected" from the pin when the pin is an input. They
probably use a bilateral switch, but even this has parasitic diodes
to the supply rails, unless some kind of magic is used.
Ever wonder how the ICL7660 or a MAX232 works to create the negative
voltage with all the parasitic diodes in a CMOS circuit??? Magic.
Jeff
--- In l..., "Danish Ali" wrote: >
> There's a further complication: most of the "5V tolerant as input"
> pins can also be used as digital outputs.
>
> A digital output normally has a PMOS transistor between Vdd3.3
> and the pin. When Vdd3.3 is not powered, this transistor will also conduct. >
> I'm not sure how the structure is changed for a 5V-tolerant pin.
> But this is one reason why the fully-I2C-compatible pins are
> open-drain - they do not have the PMOS transistor and so they
> _are_ 5V-tolerant even when the processor is not powered
> (part of the I2C spec is that a non-powered device should not
> crowbar the signal lines).
>
> Regards,
> Danish
> --- In l..., "ksdoubleshooter" wrote:
> >
> > There is a lot of misinformation going on in this thread. I've been > > involved in the design of 3 custom CMOS ASIC's
and I know CMOS
> > processes.
> >
> > The clamp diodes on CMOS inputs are optional, however they are
> > almost universally used to protect the gate oxide. A P-well process > > was used on the ASIC's that I was involved
with. The clamp diode to > > ground was fabricated with an N+ diffusion inside
of a P-well with > > the well tied to ground. The clamp diode to Vdd was
a P+ diffusion > > into the N- substrate. This P+ diffusion was long,
skinny and folded > > so that it provided series resistance and a clamp
to Vdd.
> >
> > Someone in the thread referred to these diodes as body diodes. That > > is not correct. Body diodes are the parasitic
diodes that are formed > > between drain/substrate and source/substrate
connnections.
> >
> > Someone also referred to the potential to overheat the input clamp > > diodes with too much current. This will not happen
-- something much > > worse will happen. All CMOS processes that I am
aware of have a
> > parasitic thyristor. Triggering this thyristor into conduction is
> > the dreaded "latch up condition" This thyristor is triggered by too > > much current into either of the input clamp
diodes.
> >
> > 5 volt tolerant inputs are usually fabricated with an n-channel
> > device, where the gate and source are tied to ground and the drain > > is tied to the input through some series
resistance. The break down > > of the body diode provides the clamping at some
voltage above 5
> > volts.
> >
> > Jeff
>
Reply by Tom Walsh●September 25, 20072007-09-25
ksdoubleshooter wrote: >
> There is a lot of misinformation going on in this thread. I've been
> involved in the design of 3 custom CMOS ASIC's and I know CMOS
> processes.
>
> The clamp diodes on CMOS inputs are optional, however they are
> almost universally used to protect the gate oxide. A P-well process
> was used on the ASIC's that I was involved with. The clamp diode to
> ground was fabricated with an N+ diffusion inside of a P-well with
> the well tied to ground. The clamp diode to Vdd was a P+ diffusion
> into the N- substrate. This P+ diffusion was long, skinny and folded
> so that it provided series resistance and a clamp to Vdd.
>
Thank you! That information is very interesting, I've often wondered
about the magical world of die-making. :-)
TomW
> Someone in the thread referred to these diodes as
body diodes. That
> is not correct. Body diodes are the parasitic diodes that are formed
> between drain/substrate and source/substrate connnections.
>
> Someone also referred to the potential to overheat the input clamp
> diodes with too much current. This will not happen -- something much
> worse will happen. All CMOS processes that I am aware of have a
> parasitic thyristor. Triggering this thyristor into conduction is
> the dreaded "latch up condition" This thyristor is triggered by too
> much current into either of the input clamp diodes.
>
> 5 volt tolerant inputs are usually fabricated with an n-channel
> device, where the gate and source are tied to ground and the drain
> is tied to the input through some series resistance. The break down
> of the body diode provides the clamping at some voltage above 5
> volts.
>
> Jeff
>
> --- In lpc2000@yahoogroups .com ,
> Robert Adsett
> wrote:
> >
> > At 11:26 PM 9/24/2007 +0000, rtstofer wrote:
> > >That's correct for the input. The fine print note about Vdd being
> > >present is the issue at hand. If there is no supplied Vdd to
> sink the
> > >excess voltage from the body diodes then 5.0 - Vf becomes Vdd and
> the
> > >core can't handle that voltage.
> > >
> > >It's just a design issue to be certain that any external gadgets
> don't
> > >get 5V before the chip gets Vdd. I suspect even a few
> microseconds
> > >could be bad.
> >
> > Not that I'd recommend it but I've run the core at 5V for
longer
> than that
> > (seconds) accidentally when checking power sequencing behaviour
> with no
> > apparent side effects. There may well be long term consequences
> from doing
> > that but it didn't appear to be immediately catastrophic.
> >
> > Robert
> >
> > http://www.aeolusde velopment. com/
> >
> > From the Divided by a Common Language File (Edited to protect the
> guilty)
> > ME - "I'd like to get Price and delivery for connector Part #
> XXXXX"
> > Dist./Rep - "$X.XX Lead time 37 days"
> > ME - "Anything we can do about lead time? 37 days seems a bit
> high."
> > Dist./Rep - "that is the lead time given because our stock is
> live.... we
> > currently have stock."
> > --
Tom Walsh - WN3L - Embedded Systems Consultant http://openhardware.nethttp://cyberiansoftware.comhttp://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
Reply by Danish Ali●September 25, 20072007-09-25
There's a further complication: most of the "5V tolerant as input"
pins can also be used as digital outputs.
A digital output normally has a PMOS transistor between Vdd3.3
and the pin. When Vdd3.3 is not powered, this transistor will also conduct.
I'm not sure how the structure is changed for a 5V-tolerant pin.
But this is one reason why the fully-I2C-compatible pins are
open-drain - they do not have the PMOS transistor and so they
_are_ 5V-tolerant even when the processor is not powered
(part of the I2C spec is that a non-powered device should not
crowbar the signal lines).
Regards,
Danish
--- In l..., "ksdoubleshooter" wrote: >
> There is a lot of misinformation going on in this thread. I've been
> involved in the design of 3 custom CMOS ASIC's and I know CMOS
> processes.
>
> The clamp diodes on CMOS inputs are optional, however they are
> almost universally used to protect the gate oxide. A P-well process
> was used on the ASIC's that I was involved with. The clamp diode to
> ground was fabricated with an N+ diffusion inside of a P-well with
> the well tied to ground. The clamp diode to Vdd was a P+ diffusion
> into the N- substrate. This P+ diffusion was long, skinny and folded
> so that it provided series resistance and a clamp to Vdd.
>
> Someone in the thread referred to these diodes as body diodes. That
> is not correct. Body diodes are the parasitic diodes that are formed
> between drain/substrate and source/substrate connnections.
>
> Someone also referred to the potential to overheat the input clamp
> diodes with too much current. This will not happen -- something much
> worse will happen. All CMOS processes that I am aware of have a
> parasitic thyristor. Triggering this thyristor into conduction is
> the dreaded "latch up condition" This thyristor is triggered by too
> much current into either of the input clamp diodes.
>
> 5 volt tolerant inputs are usually fabricated with an n-channel
> device, where the gate and source are tied to ground and the drain
> is tied to the input through some series resistance. The break down
> of the body diode provides the clamping at some voltage above 5
> volts.
>
> Jeff
Reply by ksdoubleshooter●September 25, 20072007-09-25
There is a lot of misinformation going on in this thread. I've been
involved in the design of 3 custom CMOS ASIC's and I know CMOS
processes.
The clamp diodes on CMOS inputs are optional, however they are
almost universally used to protect the gate oxide. A P-well process
was used on the ASIC's that I was involved with. The clamp diode to
ground was fabricated with an N+ diffusion inside of a P-well with
the well tied to ground. The clamp diode to Vdd was a P+ diffusion
into the N- substrate. This P+ diffusion was long, skinny and folded
so that it provided series resistance and a clamp to Vdd.
Someone in the thread referred to these diodes as body diodes. That
is not correct. Body diodes are the parasitic diodes that are formed
between drain/substrate and source/substrate connnections.
Someone also referred to the potential to overheat the input clamp
diodes with too much current. This will not happen -- something much
worse will happen. All CMOS processes that I am aware of have a
parasitic thyristor. Triggering this thyristor into conduction is
the dreaded "latch up condition" This thyristor is triggered by too
much current into either of the input clamp diodes.
5 volt tolerant inputs are usually fabricated with an n-channel
device, where the gate and source are tied to ground and the drain
is tied to the input through some series resistance. The break down
of the body diode provides the clamping at some voltage above 5
volts.
Jeff
--- In l..., Robert Adsett
wrote: >
> At 11:26 PM 9/24/2007 +0000, rtstofer wrote:
> >That's correct for the input. The fine print note about Vdd being
> >present is the issue at hand. If there is no supplied Vdd to sink the > >excess voltage from the body diodes then 5.0 - Vf
becomes Vdd and the > >core can't handle that voltage.
> >
> >It's just a design issue to be certain that any external gadgets don't > >get 5V before the chip gets Vdd. I suspect even a
few microseconds > >could be bad.
>
> Not that I'd recommend it but I've run the core at 5V for longer than that > (seconds) accidentally when checking power sequencing
behaviour with no > apparent side effects. There may well be long term
consequences from doing > that but it didn't appear to be immediately
catastrophic.
>
> Robert
>
> http://www.aeolusdevelopment.com/
>
> From the Divided by a Common Language File (Edited to protect the guilty) > ME - "I'd like to get Price and delivery for
connector Part # XXXXX" > Dist./Rep - "$X.XX Lead time 37 days"
> ME - "Anything we can do about lead time? 37 days seems a bit high." > Dist./Rep - "that is the lead time given because our
stock is live.... we > currently have stock."
>
Reply by rtstofer●September 24, 20072007-09-24
--- In l..., "jsm09a"
wrote: > > Regardless of how they clamp, the voltage continues
into the core at a
> > high level. The more series diodes, the higher that voltage can get.
>
> Sorry, I don't follow "voltage continues into the core". Assuming
> that the port was configured as an input, my understanding would be
> that extremely little input current would "continue into the core".
> On the data sheet, under Static Characteristics, pull-up current (Ipu)
> is shown
> as zero microamps when the port input voltage is anywhere from 3.3V to 5V. >
That's correct for the input. The fine print note about Vdd being
present is the issue at hand. If there is no supplied Vdd to sink the
excess voltage from the body diodes then 5.0 - Vf becomes Vdd and the
core can't handle that voltage.
It's just a design issue to be certain that any external gadgets
don't
get 5V before the chip gets Vdd. I suspect even a few microseconds
could be bad.
Richard
Reply by Robert Adsett●September 24, 20072007-09-24
At 11:26 PM 9/24/2007 +0000, rtstofer wrote: >That's correct for the input. The fine print
note about Vdd being
>present is the issue at hand. If there is no supplied Vdd to sink the
>excess voltage from the body diodes then 5.0 - Vf becomes Vdd and the
>core can't handle that voltage.
>
>It's just a design issue to be certain that any external gadgets
don't
>get 5V before the chip gets Vdd. I suspect even a few microseconds
>could be bad.
Not that I'd recommend it but I've run the core at 5V for longer than
that
(seconds) accidentally when checking power sequencing behaviour with no
apparent side effects. There may well be long term consequences from doing
that but it didn't appear to be immediately catastrophic.
From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live.... we
currently have stock."
Reply by Tom Walsh●September 24, 20072007-09-24
jsm09a wrote: >
> --- In lpc2000@yahoogroups .com ,
> Tom Walsh wrote:
>
> > Ok, lets understand what happens with "5V Tolerant Pins" when
> connecting
> > such pins to a processor that uses a lower I/O supply (e.g. 3.3volts).
> > The extra voltage has to go somewhere. At worst case, you have
> > 1.2volts, at so many milli / micro amperes of current that has to go
> > someplace. Where does it go?
> >
> > The excess power (watts) gets dumped into the 3.3volt supply via
> > clamping diodes placed at the processor pin and are connected to the
> I/O
> > supply rail. While the power is low (watts) and the 3.3volt supply can
> > handle dissipating the excess power, a problem may occur at the
> > processor pin area of the silicon. The wattage being dumped across the
> > clamping diode shows up as heat. Too much heat will degrade the
> > lifetime of the silicon faster than the silicon would normally age.
> >
> > The amount of heat generated depends on the source resistance of the
> > 5volt gate / device / whatever that is connected to that processor
> pin.
> > Too low a source resistance and POOF(!), you let out the magic-smoke.
>
> Hi Tom,
>
> I believe that you are assuming that there is a single clamping diode
> from GPIO pin to the 3.3V rail and that the current must be limited by
> the external impedance. I have not found any documentation that would
> confirm that to be the case.
>
> In fact, since they do not specify a maximum input current for the
> GPIO pins, I strongly suspect that this is not the case. In other
> words, I believe that you could tie a GPIO pin directly to a 5V rail
> and not experience any heat/damage.
>
> My guess is that they have a "string" of diodes (at Vf ~0.5V each)
> that can drop 5 volts to 3.3 volts before clamping (and this would
> explain the requirement that 3.3 volts be present to allow 5V tolerance).
>
Bad guess. You are forgetting that each diode has a parameter
called If (Max Forward Current) sometimes listed as Io. Max forward
current is determined by the inherent series resistance of a given
diode. The limiting factor in the amount of current that can be carried
in the forward direction is junction temperature. Exceeed the max
junction temp and you destroy the device. e.g. Watts Law.
> There are lots of logic families (e.g. 74LVC) that
can be used for
> level translation without the need for a 5V supply rail. I see no
> reason that the LPC family could not include the same type of circuitry.
>
I do! It is called "space" The die is limited as to the area it has
for gates. Without a clear spec from NXP, you must assume the worst
case. I would think that adding a couple of transistors to each input
pin would be costly in terms of die space which could be better used to
put a larger RAM / Flash array in there.
Common practice is a clamping diode to the I/O supply rail. If you want
to make the pins truly 5volt tolerant, don't apply 5volts (or in excess
of 3.3volts) to them. Use an external zenor, or clamp diode, then
current limit with a series resistor (if needed).
