On Saturday, July 25, 2020 at 4:38:48 AM UTC-4, Uwe Bonnes wrote:
> Rick C <gnuarm.deletethisbit@gmail.com> wrote:
> > Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?  
> > 
> In single ended mode, range is 0V 0 0x000 (+/- offset, non-lineraity, etc) and +Vref = 0xfff. In differential mode, -Vref = 0xfff, 0V =0x800 and + Vref = 0xfff.
> 
> > Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is? 
> > 
> > Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?  
> > 
> > I'm thinking there must be a document somewhere that explains the ADC in more detail?  
> >
> 
> There are Applicaton notes. Look at the product page.

Thanks.  Yes, I should have looked harder for app notes.  Found them.  They even have one specifically on getting the best accuracy conversions. 

-- 

  Rick C.

  -+ Get 1,000 miles of free Supercharging
  -+ Tesla referral code - https://ts.la/richard11209

On 25/07/2020 03:32, Rick C wrote:
> On Friday, July 24, 2020 at 5:13:50 PM UTC-4, Rick C wrote:
>> On Friday, July 24, 2020 at 8:13:18 AM UTC-4, Michael Kellett wrote:
>>> On 24/07/2020 01:11, Rick C wrote:
>>>> Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?
>>>>
>>>> Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is?
>>>>
>>>> Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?
>>>>
>>>> I'm thinking there must be a document somewhere that explains the ADC in more detail?
>>>>
>>>
>>> I've used lots of different STM32xxxx processors and their ADCs, some of
>>> them specify the internal resistance in the mpx as well as the sample cap.
>>> In your part the sample cap is 5pF but they don't spec the mpx
>>> resistance -  the RAIN table should enable you to work it out but it
>>> seems a bit odd:
>>> If you try to calculate the internal mpx resistance from the data given
>>> for two different sampling times it varies according to which pairyou pick.
>>>
>>> Sampling cycle in the table is the number of ADC clock samples set for
>>> the sampling time.
>>>
>>> If you are going to sample fast at a high rate you need to buffer with a
>>> decently fast op amp.
>>>
>>> If you will only sample fast but at a low rate per channel you can get
>>> away with a capacitor across the the input.
>>>
>>>   From my experience with these ADCs, assume poor linearity close to the
>>> rails (and in my case that also means Vref- as well.)
>>>
>>> I've used ST ADCs with 470k input resistors and a big cap, but only
>>> where I sample quite infrequently.
>>>
>>> This is a fairly recent iteration of STs ADC and my main experience is
>>> with the 16 bit version - which is pretty good if you drive it with a
>>> proper LT differential ADC driver.
>>>
>>> How fast do you want to sample - this thing seems quite forgiving in
>>> terms of source resistance demand, 4k7 at 865ksamples/second. The core
>>> doesn't have to wait - it has all sorst of fancy DMA and buffering and
>>> averaging stuff in the hardware.
>>>
>>> You can try ST's forums but you'll get  a better answer quicker if you
>>> buy a Nucleo board and try it.
>>
>> I had typed a rather lengthy reply, then Firefox crashed.  lol
>>
>> In short, our use will be for low duty cycle readings, perhaps as fast as 1 kSPS unless we oversample.  We are measuring airflow and integrating to obtain volume.  That measurement might be oversampled by 16 so we can do a bit of averaging.  Still, that is well below 125 kHz, so we should be good... unless someone wants to over sample all the signals.  lol
>>
>> So if we sample slowly it should be ok to use resistive dividers as long as the equivalent impedance is below 33 kohms it would appear.  No?
>>
>> Can you give me an idea of the extent of the non-linearity, but in how close to the ground rail and to what extent?  The ADC only seems to be good enough for 10 bits, so how much worse than that?
>>
>> I'll give the ST forums a try.  Thanks.
> 
> Oh yeah, there was the other issue of the input voltage range.  If the Vref+ and Vref- inputs are connected to 3.3 volts and 0 volts respectively, are those the reference points for the 4096 values of conversion with 0 at Vref- and 4095 at Vref+?
> 
> I guess I'm too used to various ADCs with internal Vref setting the conversion range.
> 

The voltage range is from 0 to Vref if thats where you connect the ref 
pins (lower pin count packages connect them internally.)

I've never measured carefully the linearity near the high and low lmits 
- it's a region to steer clear of because off offsets (at thelow end) 
and problems with drivers as well as ADC at the topend.

MK

Rick C <gnuarm.deletethisbit@gmail.com> wrote:
> Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?  
> 
In single ended mode, range is 0V 0 0x000 (+/- offset, non-lineraity, etc) and +Vref = 0xfff. In differential mode, -Vref = 0xfff, 0V =0x800 and + Vref = 0xfff.

> Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is? 
> 
> Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?  
> 
> I'm thinking there must be a document somewhere that explains the ADC in more detail?  
>

There are Applicaton notes. Look at the product page.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

On Friday, July 24, 2020 at 5:13:50 PM UTC-4, Rick C wrote:
> On Friday, July 24, 2020 at 8:13:18 AM UTC-4, Michael Kellett wrote:
> > On 24/07/2020 01:11, Rick C wrote:
> > > Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?
> > > 
> > > Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is?
> > > 
> > > Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?
> > > 
> > > I'm thinking there must be a document somewhere that explains the ADC in more detail?
> > > 
> > 
> > I've used lots of different STM32xxxx processors and their ADCs, some of 
> > them specify the internal resistance in the mpx as well as the sample cap.
> > In your part the sample cap is 5pF but they don't spec the mpx 
> > resistance -  the RAIN table should enable you to work it out but it 
> > seems a bit odd:
> > If you try to calculate the internal mpx resistance from the data given 
> > for two different sampling times it varies according to which pairyou pick.
> > 
> > Sampling cycle in the table is the number of ADC clock samples set for 
> > the sampling time.
> > 
> > If you are going to sample fast at a high rate you need to buffer with a 
> > decently fast op amp.
> > 
> > If you will only sample fast but at a low rate per channel you can get 
> > away with a capacitor across the the input.
> > 
> >  From my experience with these ADCs, assume poor linearity close to the 
> > rails (and in my case that also means Vref- as well.)
> > 
> > I've used ST ADCs with 470k input resistors and a big cap, but only 
> > where I sample quite infrequently.
> > 
> > This is a fairly recent iteration of STs ADC and my main experience is 
> > with the 16 bit version - which is pretty good if you drive it with a 
> > proper LT differential ADC driver.
> > 
> > How fast do you want to sample - this thing seems quite forgiving in 
> > terms of source resistance demand, 4k7 at 865ksamples/second. The core 
> > doesn't have to wait - it has all sorst of fancy DMA and buffering and 
> > averaging stuff in the hardware.
> > 
> > You can try ST's forums but you'll get  a better answer quicker if you 
> > buy a Nucleo board and try it.
> 
> I had typed a rather lengthy reply, then Firefox crashed.  lol 
> 
> In short, our use will be for low duty cycle readings, perhaps as fast as 1 kSPS unless we oversample.  We are measuring airflow and integrating to obtain volume.  That measurement might be oversampled by 16 so we can do a bit of averaging.  Still, that is well below 125 kHz, so we should be good... unless someone wants to over sample all the signals.  lol 
> 
> So if we sample slowly it should be ok to use resistive dividers as long as the equivalent impedance is below 33 kohms it would appear.  No? 
> 
> Can you give me an idea of the extent of the non-linearity, but in how close to the ground rail and to what extent?  The ADC only seems to be good enough for 10 bits, so how much worse than that? 
> 
> I'll give the ST forums a try.  Thanks.

Oh yeah, there was the other issue of the input voltage range.  If the Vref+ and Vref- inputs are connected to 3.3 volts and 0 volts respectively, are those the reference points for the 4096 values of conversion with 0 at Vref- and 4095 at Vref+?  

I guess I'm too used to various ADCs with internal Vref setting the conversion range. 

-- 

  Rick C.

  -- Get 1,000 miles of free Supercharging
  -- Tesla referral code - https://ts.la/richard11209

On Friday, July 24, 2020 at 8:13:18 AM UTC-4, Michael Kellett wrote:
> On 24/07/2020 01:11, Rick C wrote:
> > Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?
> > 
> > Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is?
> > 
> > Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?
> > 
> > I'm thinking there must be a document somewhere that explains the ADC in more detail?
> > 
> 
> I've used lots of different STM32xxxx processors and their ADCs, some of 
> them specify the internal resistance in the mpx as well as the sample cap.
> In your part the sample cap is 5pF but they don't spec the mpx 
> resistance -  the RAIN table should enable you to work it out but it 
> seems a bit odd:
> If you try to calculate the internal mpx resistance from the data given 
> for two different sampling times it varies according to which pairyou pick.
> 
> Sampling cycle in the table is the number of ADC clock samples set for 
> the sampling time.
> 
> If you are going to sample fast at a high rate you need to buffer with a 
> decently fast op amp.
> 
> If you will only sample fast but at a low rate per channel you can get 
> away with a capacitor across the the input.
> 
>  From my experience with these ADCs, assume poor linearity close to the 
> rails (and in my case that also means Vref- as well.)
> 
> I've used ST ADCs with 470k input resistors and a big cap, but only 
> where I sample quite infrequently.
> 
> This is a fairly recent iteration of STs ADC and my main experience is 
> with the 16 bit version - which is pretty good if you drive it with a 
> proper LT differential ADC driver.
> 
> How fast do you want to sample - this thing seems quite forgiving in 
> terms of source resistance demand, 4k7 at 865ksamples/second. The core 
> doesn't have to wait - it has all sorst of fancy DMA and buffering and 
> averaging stuff in the hardware.
> 
> You can try ST's forums but you'll get  a better answer quicker if you 
> buy a Nucleo board and try it.

I had typed a rather lengthy reply, then Firefox crashed.  lol 

In short, our use will be for low duty cycle readings, perhaps as fast as 1 kSPS unless we oversample.  We are measuring airflow and integrating to obtain volume.  That measurement might be oversampled by 16 so we can do a bit of averaging.  Still, that is well below 125 kHz, so we should be good... unless someone wants to over sample all the signals.  lol 

So if we sample slowly it should be ok to use resistive dividers as long as the equivalent impedance is below 33 kohms it would appear.  No? 

Can you give me an idea of the extent of the non-linearity, but in how close to the ground rail and to what extent?  The ADC only seems to be good enough for 10 bits, so how much worse than that? 

I'll give the ST forums a try.  Thanks.

-- 

  Rick C.

  + Get 1,000 miles of free Supercharging
  + Tesla referral code - https://ts.la/richard11209

On 24/07/2020 01:11, Rick C wrote:
> Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?
> 
> Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is?
> 
> Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?
> 
> I'm thinking there must be a document somewhere that explains the ADC in more detail?
> 

I've used lots of different STM32xxxx processors and their ADCs, some of 
them specify the internal resistance in the mpx as well as the sample cap.
In your part the sample cap is 5pF but they don't spec the mpx 
resistance -  the RAIN table should enable you to work it out but it 
seems a bit odd:
If you try to calculate the internal mpx resistance from the data given 
for two different sampling times it varies according to which pairyou pick.

Sampling cycle in the table is the number of ADC clock samples set for 
the sampling time.

If you are going to sample fast at a high rate you need to buffer with a 
decently fast op amp.

If you will only sample fast but at a low rate per channel you can get 
away with a capacitor across the the input.

 From my experience with these ADCs, assume poor linearity close to the 
rails (and in my case that also means Vref- as well.)

I've used ST ADCs with 470k input resistors and a big cap, but only 
where I sample quite infrequently.

This is a fairly recent iteration of STs ADC and my main experience is 
with the 16 bit version - which is pretty good if you drive it with a 
proper LT differential ADC driver.

How fast do you want to sample - this thing seems quite forgiving in 
terms of source resistance demand, 4k7 at 865ksamples/second. The core 
doesn't have to wait - it has all sorst of fancy DMA and buffering and 
averaging stuff in the hardware.

You can try ST's forums but you'll get  a better answer quicker if you 
buy a Nucleo board and try it.

MK

Maybe someone can help me out with this.  I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced.  It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails.  With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input produce a code of 0 and 3.3 volts on the input produce a code of 0xFFF and 1.65 volts produce 0x3FF?  

Then there are the input circuits.  Table 75 says Rain is 50 kohm max.  Then table 76 lists Rain max of various values from 100 ohms up.  So do fast conversions really require such low output impedances from the driving circuits?  Table 76 has a column without units indicated, Sampling Cycle @80 MHz.  Any idea what that is? 

Lastly there is mention of an internal op amp.  Is there any way to insert this between the input mux and the ADC so that every input won't need a driver if we are sampling fast?  

I'm thinking there must be a document somewhere that explains the ADC in more detail?  

-- 

  Rick C.

  - Get 1,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209