Thanks for the ideas, however I don't think any of them are the current
problem.
The Reset line goes from the BDM connector to the processor and to a resistor
to
a Motorola MC33989 System Basis Chip to control the reset. I removed the
resistor to the SBC to no avail. Except that the board wouldn't run
properly
WITHOUT the debugger connected anymore -- as you might expect with a slow VDD
rise, the reset line goes high before VDD is up so maybe we don't get a
clean
reset. Not a problem with the SBC reconnected. By the way, the identical
circuitry works fine on two other boards that don't have the slow VDD rise
(and
they use H256 or DP256 processors instead of D64).
MODA and MODB are tied to ground and not used for any other purpose.
There is a 10K pullup resistor on the BDM line. I tried it with and without
the
resistor and there's no difference.
One more thing: Once we finally do get code loaded into the processor, if not
only runs fine, but seems to be easier to reprogram. It can take 10 tries and
a
bunch of manual resets to get the debugger running the first time, but rarely
more than three tries to load revised code into the processor. This behavior
has
been consistent through eight boards now!! I'm baffled.
On the bright side, it doesn't really seem to have anything to do with a
slow
VDD rise time. That's good, 'cause I had NO idea how to fix that!
thanks,
Pat
Doron Fael wrote:
> Pat,
>
> Here are a few possible causes for your BDM startup problems:
>
> 1)
> Make sure nothing interferes with the Reset coming from the BDM
connector.
> It should be connected directly to your HCS12 CPU in order to Reset, and
> un-Reset it when it needs to.
>
> 2)
> A BDM must bring up the HCS12 CPU in Special Single Chip mode first, and
> can then switch to any desired operating mode by writing to some
internal
> registers. In order for this to happen, it is required that MODA and
MODB
> will be held low during Reset. If you have something to drive one of
these
> signals high during Reset, you will have problems. If you have nothing
> connected to MODA and MODB, they will be held low during Reset by
internal
> HCS12 pull-down resistors that are enabled during Reset.
>
> 3)
> The BKGD pin should be connected directly from the BDM connector to the
CPU.
>
> Hope this helps,
> Doron
> Nohau Corporation
> HC12 In-Circuit Emulators
> www.nohau.com/emul12pc.html
>
> At 01:36 PM 4/11/2003 -0600, you wrote:
>
> >Hi list,
> >
> >Does anyone out there know if there are any issues with a slow rise
time
> >on VDD for
> >the HCS12 processor family (D64 processor in particular)? I
haven't found
> >anything
> >about it in the datasheet.
> >
> >Due to the large amount of capacitance on the power bus in one of
our
> >systems, the
> >12V supply rises slowly, hence the output of the 5V regulator also
rises
> >slowly. It
> >takes about 15 ms to get from 0 to 4.75 volts. Is there any reason
that
> >this should
> >upset the processor? We're having trouble getting it to
acknowledge BDM
> >communication at power up, though it always seems to execute code
> >correctly once we
> >finally get it loaded. The clock looks to be running fine. Oh yeah,
the
> >reset line
> >is held firmly low until VDD has been at 5 volts (+/- 100 mv, maybe)
for
> >800 us or
> >so.
> >
> >Thoughts appreciated,
> >
> >Pat
>
>
> --------------------
>
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