Following up to my own posting is bad style, sorry, but I had to correct the Fmax ...

Tommy Thorn wrote: Martin Schoeberl wrote:You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.
What in particular?

Alas, the only fairly complete clone was not been optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to that?
I dug it out again and either my memory was bad or Quartus has improved. A complete (but unoptimized) system with UART, 640x480x1 video and other stuff takes 9,294 LE (46 %) and clocks in at 70 MHz in a EP1C20-C7. Knowing how much there is that could be improved with a completely rewritten pipeline, I wonder what the performance could ultimately be. BTW it does have a 16 KiB I$, but no D$.

Tommy

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> An instruction cache is definitely a must (all my clones have one), but it isn't trivial to make it such that it isn't tailor made
> for a particularly FPGA.

yes, that's true. I have vendor specific files for this.

>
> The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't
> come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need
> for other peripherals. Did LEON have a good solution here?

Again agree. Wishbone has a combinatorial path from the master
request to the slave ack which makes it very hard to place
registers for address and data at the FPGA pins (using some
pipelining for the memory interface). First I added another
signal to the WB. Later I decided to roll my own interconnection
interface, which I called SimpCon:
http://www.opencores.org/projects.cgi/web/simpcon/overview

LEON uses the AMBA bus.

Martin

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Martin Schoeberl wrote:Plasma was about 40 MHz in a Cyclone 1C12. However, the main issue
was the not very well designed memory interface. And the core
had no caches at all! That's a performance killer for a pipelined
RISC.

An instruction cache is definitely a must (all my clones have one), but it isn't trivial to make it such that it isn't tailor made for a particularly FPGA.

The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need for other peripherals. Did LEON have a good solution here?

I'll post my ALU in a different thread.

Cheers,
Tommy

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> Alas, the only fairly complete clone was not been optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to
> that?
>

Plasma was about 40 MHz in a Cyclone 1C12. However, the main issue
was the not very well designed memory interface. And the core
had no caches at all! That's a performance killer for a pipelined
RISC.

> I later understood an alternative to stalling for interdependencies: late detect and "lazy" flushing. The experimental prototype
> based on this was completely dominated by the ALU, seeing 90 - 130 MHz (1C20) depending on how many stages I used for the ALU.
> IIRC, the rest of the pipe was about 6 stages. I'd love to complete this to the point where it can boot Linux, but I have other
> priorities today.

ok, cool - that's the frequency range of the NISO.

> Ah, but doesn't LEON include a complete MMU? Even without it, I think it is much much larger than my clone, MB, and Nios II.

Yes, it's larger: about 8000 LCs compared to the 2000 LCs of a NIOS.

Martin

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Martin Schoeberl wrote:You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.
What in particular?

Alas, the only fairly complete clone was not been optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to that?

I later understood an alternative to stalling for interdependencies: late detect and "lazy" flushing. The experimental prototype based on this was completely dominated by the ALU, seeing 90 - 130 MHz (1C20) depending on how many stages I used for the ALU. IIRC, the rest of the pipe was about 6 stages. I'd love to complete this to the point where it can boot Linux, but I have other priorities today.

I should post the ALU (which was based on the article on the Nios I ALU). Maybe someone with extensive experience with a Java processor could suggest improvements ;-)

LEON is, in my opinion, the most professional and free RISC
for an FPGA. Got it running in a few days on my Cyclone FPGA
board.
Ah, but doesn't LEON include a complete MMU? Even without it, I think it is much much larger than my clone, MB, and Nios II.

Professional and free rarely go together. To get to the polish level of LEON is quite a lot of work.

All the best,
Tommy

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Eric Smith wrote:
If you're happy doing that, why do you care about MicroBlaze?

I care about all available soft cores and want to understand how they compare.

My question was spurred by Richard's "One advantage of the MicroBlaze is the software development suite." comment, which you apparently agree isn't that special.

Interesting, it looks like MIPS' infamous '976 patent has finally
expired. Until that happened, you had to leave out the unaligned
load and store instructions if you wanted to keep that army of
lawyers at bay.

The unaligned load and store instructions (LWR, LWL, etc) only matters for existing code, but were talking embedded applications here where all code is compiled from source. The GNU tool chain will never generate the offending instructions. Keep your data aligned and you'll never miss them. Finally, they constrain the implementation, so I'd never include them.

Regards,
Tommy

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> For DIYers, a MIPS clone is the best option I've found as it's the smallest, simplest, and cleanest among the 32-bit targets
> supported by the GNU tool chain which doesn't have an army of lawyers ready to take you out at the first given opportunity
> (witness all the shut down ARM clones). Like many, I have rolled a few MIPS clones myself and building cross tools gcc, binutils,
> and newlib is not that hard. With a bit more work gdb will be there also. I don't seem to miss anything there.

You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.

LEON is, in my opinion, the most professional and free RISC
for an FPGA. Got it running in a few days on my Cyclone FPGA
board.

Martin

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Hi Richard,

> I was under the impression that the Microblaze development suite
> included a C compiler and the rest of the toolchain.

Yes, it does include a C compiler and the rest of the toolchain. It's also
capable of C++.

Regards,

Austin

> For DIYers, a MIPS clone is the best option I've found as it's the
smallest, simplest, and cleanest among the 32-bit targets supported by
the GNU tool chain which doesn't have an army of lawyers ready to take
you out at the first given opportunity (witness all the shut down ARM
clones). Like many, I have rolled a few MIPS clones myself and
building cross tools gcc, binutils, and newlib is not that hard. With
a bit more work gdb will be there also. I don't seem to miss anything
there.
>
> Regards,
> Tommy

I was under the impression that the Microblaze development suite
included a C compiler and the rest of the toolchain. Since I don't
have someone else paying the bills, I haven't pursued it.

There is another clone around that used the LCC retargetable C compiler.

I think the reason I have walked around the MIPS clones is that they
don't (and can't for copyright reasons) implement the entire
instruction set. They omit byte aligned loads or some such thing.
Maybe it's a patent thing...

I wasn't sure that the GNU toolchain would understand that it couldn't
emit instructions that weren't implemented.

Richard

> Having never used MicroBlaze, I'm curious about what makes the software
> development suite so special?

The only thing that comes to mind is the MDM core which provides debug
support through the same JTAG cable used to load the FPGA. It's possible
to do that for your own core design, but not trivial.

The main "special" thing about the development suite is the configuration
of the hardware, not the software.

> For DIYers, a MIPS clone is the best option I've found as it's the
> smallest, simplest, and cleanest among the 32-bit targets supported by the
> GNU tool chain

If you're happy doing that, why do you care about MicroBlaze?

> which doesn't have an army of lawyers ready to take you out
> at the first given opportunity (witness all the shut down ARM clones).

Interesting, it looks like MIPS' infamous '976 patent has finally
expired. Until that happened, you had to leave out the unaligned
load and store instructions if you wanted to keep that army of
lawyers at bay.

Eric