> From a device design standpoint it makes good
sense that these
> pins be open drain output and with hindsight it is now crystal clear,
> (:/).
>
> Thanks again!
>
> Tom Alldread
>
I don't think it is clearly specified but note [3] starts by stating
"Open-drain 5V tolerant digitial I/O..." and the second sentence
starts "It requires external pull-up...". What it fails to state is
that the pins require pull-up regardless of the function (GPIO, I2C or
MATxxx).
There have been many posts on this forum re: these I2C pins. SSEL is
the other commonly misunderstood pin which, depending entirely on the
device, may have to be pulled high and not used as GPIO even when the
SPI gadget is never a slave. On other devices it can be used as GPIO
as long as the gadget is a master.
--- In l..., "rtstofer" wrote: >
> --- In l..., "tmasyl" wrote:
> >
> > Greetings:
> >
> > I noticed the LPC2103, P0.3 and P0.18 GPIO pins, which can
> > alternately be control block assigned to I2C SDA data pin functions,
> > require pull up resistors when set to GPIO output mode. I also noticed
> > that other 5 Volt Tolerant pins do not appear to need pullups. Are the
> > alternate I2C SDA pins of unique design compared to the rest -
> > possibly conventional open drain without internal pullups?
>
> The I2C bus always requires pull-up resistors because it is a
> multi-master bus. Any device needs to be able to pull the clock or
> data signal low.
>
> Other pins, unless stated otherwise, have active pull-up and active
> pull-down.
>
> When a pin is designated as 5V tolerant and is not open drain, the
> voltage level at an input pin may rise to 5V but the excess voltage is
> clamped internally to the Vdd rail. This also means, as the User
> Manual or Data Sheet point out, that Vdd must be present for the pin
> to be 5V tolerant. See Note 6 to Table 4 in Section 7 of the Datasheet.
>
> For outputs, the pin voltage won't go to 5V but it will go high enough
> to work as a logic one for various families of 5V logic. See Table 6
> Section 8 - Static Characteristics of the Datasheet. Look for Voh.
>
> I have not seen a document with more detailed information re: the pin
> design.
>
> Richard
> Hi Richard:
Thank you for the clarifications!
I understand the need for an open drain output for the I2C pin
but I find the data sheet documentation seems less than clear. For
example the pin description given in table 3 for P0.3 clearly states
that when the pin is selected by the pin connect block (PCB) for I2C
operation that it has an "Open-drain output". Alternately for the GPIO
PCB selection it is just described as "General purpose Input/output
digital pin (GPIO)" which is exactly the same description given for
rest of the I/O pins with totem pole outputs. It tends to leave the
impression that the pin operates open drain in I2C mode and as a
regular totem pole pin in GPIO mode.
Possibly NXP should give future consideration to providing a
more distinguishing description for the GPIO mode I2C pins to
something like:
"General purpose Input/output open-drain digital pin (GPIO)"
I did notice the subscript 3 beside the package pin number
referring to note 3 which explains open drain output is provided for
I2C mode compatibility. But it is not clear that it retains open drain
functionality when used in GPIO mode. If the pin description also
mentioned open drain for the GPIO PCB selection then the note 3
comment would suffice.
Adding to the confusion the P0.2 pin, which is also described as
open-drain for I2C operation, exhibits different characteristics than
P0.3 in GPIO output mode. In GPIO mode P0.2 provides an active high
output voltage however P0.3 does not. Since I didn't have much load on
the P0.2 pin when testing it may just be from an internal hi Z pull up
source.
From a device design standpoint it makes good sense that these
pins be open drain output and with hindsight it is now crystal clear,
(:/).
Thanks again!
Tom Alldread
Reply by tmasyl●November 5, 20072007-11-05
Greetings:
I noticed the LPC2103, P0.3 and P0.18 GPIO pins, which can
alternately be control block assigned to I2C SDA data pin functions,
require pull up resistors when set to GPIO output mode. I also noticed
that other 5 Volt Tolerant pins do not appear to need pullups. Are the
alternate I2C SDA pins of unique design compared to the rest -
possibly conventional open drain without internal pullups?
I could not find detailed information on the design of the
LPC2103 I/O pins in the User's Manual. I was hoping to find block
diagrams for the different LPC I/O pin types. Can anyone here point me
to an NXP document that describes the different LPC I/O pin types in
detail?
