Joe,
Here is my source file for the lpc935 it is most likely not complete
and I have built it up over a few projects. But it might help it is a
mixture of philips and intel register names but it works for me.
*********************cut*below*here*********************************
#ifndef P89LPC935_H
#define P89LPC935_H
sfr at 0xE0 ACC;
sfr at 0x8e ADCON0;
#define ENBI0 0x80
#define ENADCI0 0x40
#define TMM0 0x20
#define EDGE0 0x10
#define ADCI0 0x08
#define ENADC0 0x04
#define ADCS01 0x02
#define ADCS00 0x01
sfr at 0x97 ADCON1;
#define ENBI1 0x80
#define ENADCI1 0x40
#define TMM1 0x20
#define EDGE1 0x10
#define ADCI1 0x08
#define ENADC1 0x04
#define ADCS11 0x02
#define ADCS10 0x01
sfr at 0xa3 ADINS;
sfr at 0xc0 ADMODA;
sfr at 0xa1 ADMODB;
sfr at 0xbb AD0BH;
sfr at 0xa6 AD0BL;
sfr at 0xc5 AD0DAT0;
sfr at 0xc6 AD0DAT1;
sfr at 0xc7 AD0DAT2;
sfr at 0xf4 AD0DAT3;
sfr at 0xc4 AD1BL;
sfr at 0xbc AD1BH;
sfr at 0xD5 AD1DAT0;
sfr at 0xD6 AD1DAT1;
sfr at 0xd7 AD1DAT2;
sfr at 0xf5 AD1DAT3;
sfr at 0xa2 AUXR1;
sfr at 0xf0 B;
sfr at 0xbe BRG0;
sfr at 0xbf BRG1;
sfr at 0xbd BRGCON;
sfr at 0xea CCCRA;
sfr at 0xeb CCCRB;
sfr at 0xec CCCRC;
sfr at 0xed CCCRD;
sfr at 0xac CMP1;
sfr at 0xad CMP2;
sfr at 0xf1 DEECON;
sfr at 0xf2 DEEDAT;
sfr at 0xf3 DEEADR;
sfr at 0x95 DIVM;
sfr at 0x83 DPH;
sfr at 0x82 DPL;
sfr at 0xe7 FMADRH;
sfr at 0xe6 FMADRL;
sfr at 0xe4 FMCON;
sfr at 0xe5 FMDAT;
sfr at 0xdb I2ADR;
sfr at 0xd8 I2CON;
sfr at 0xda I2DAT;
sfr at 0xdd I2SCLH;
sfr at 0xdc I2SCLL;
sfr at 0xd9 I2STAT;
sfr at 0xab ICRAH;
sfr at 0xaa iCRAL;
sfr at 0xaf ICRBH;
sfr at 0xae ICRBL;
sfr at 0xa8 IEN0;
sfr at 0xe8 IEN1;
sfr at 0xB8 IP0;
sfr at 0xb7 IP0H;
sfr at 0xf8 IP1;
sfr at 0xf7 IP1H;
sfr at 0x94 KBCON;
sfr at 0x86 KBMASK;
sfr at 0x93 KBPATN;
sfr at 0xef OCRAH;
sfr at 0xee OCRAL;
sfr at 0xfb OCRBH;
sfr at 0xfa OCRBL;
sfr at 0xfd OCRCH;
sfr at 0xfc OCRCL;
sfr at 0xff OCRDH;
sfr at 0xfe OCRDL;
sfr at 0x80 P0;
sfr at 0x90 P1;
sfr at 0xa0 P2;
sfr at 0xb0 P3;
sfr at 0x84 P0M1;
sfr at 0x85 P0M2;
sfr at 0x91 P1M1;
sfr at 0x92 P1M2;
sfr at 0xa4 P2M1;
sfr at 0xa5 P2M2;
sfr at 0xb1 P3M1;
sfr at 0xb2 P3M2;
sfr at 0x87 PCON;
sfr at 0xb5 PCONA;
sfr at 0xd0 PSW;
sfr at 0xf6 PT0AD;
sfr at 0xdf RSTSRC;
sfr at 0xd1 RTCCON;
sfr at 0xd2 RTCH;
sfr at 0xd3 RTCL;
sfr at 0xa9 SADDR;
sfr at 0xb9 SADEN;
sfr at 0x99 SBUF;
sfr at 0x98 SCON;
sfr at 0xba SSTAT;
sfr at 0x81 SP;
sfr at 0xe2 SPCTL;
sfr at 0xe1 STAT;
sfr at 0xe3 SPDAT;
sfr at 0x8f TAMOD;
sfr at 0x88 TCON;
sfr at 0xc8 TCR20;
sfr at 0xf9 TCR21;
sfr at 0x8c TH0;
sfr at 0x8d TH1;
sfr at 0xcd TH2;
sfr at 0xc9 TICR2;
sfr at 0xe9 TIFR2;
sfr at 0xde TISE2;
sfr at 0x8a TL0;
sfr at 0x8b TL1;
sfr at 0xcc TL2;
sfr at 0x89 TMOD;
sfr at 0xcf TOR2H;
sfr at 0xce TOR2L;
sfr at 0xcb TPCR2H;
sfr at 0xca TPCR2L;
sfr at 0x96 TRIM;
sfr at 0xa7 WDCON;
sfr at 0xc1 WDL;
sfr at 0xc2 WFEED1;
sfr at 0xc3 WFEED2;
/* BIT Register */
/* P0 */
sbit at 0x80 P0_0;
sbit at 0x81 P0_1;
sbit at 0x82 P0_2;
sbit at 0x83 P0_3;
sbit at 0x84 P0_4;
sbit at 0x85 P0_5;
sbit at 0x86 P0_6;
sbit at 0x87 P0_7;
/* TCON */
sbit at 0x88 IT0;
sbit at 0x89 IE0;
sbit at 0x8A IT1;
sbit at 0x8B IE1;
sbit at 0x8C TR0;
sbit at 0x8D TF0;
sbit at 0x8E TR1;
sbit at 0x8F TF1;
/* P1 */
sbit at 0x90 P1_0;
sbit at 0x91 P1_1;
sbit at 0x92 P1_2;
sbit at 0x93 P1_3;
sbit at 0x94 P1_4;
sbit at 0x95 P1_5;
sbit at 0x96 P1_6;
sbit at 0x97 P1_7;
/* SCON */
sbit at 0x98 RI;
sbit at 0x99 TI;
sbit at 0x9A RB8;
sbit at 0x9B TB8;
sbit at 0x9C REN;
sbit at 0x9D SM2;
sbit at 0x9E SM1;
sbit at 0x9F SM0;
/* P2 */
sbit at 0xA0 P2_0;
sbit at 0xA1 P2_1;
sbit at 0xA2 P2_2;
sbit at 0xA3 P2_3;
sbit at 0xA4 P2_4;
sbit at 0xA5 P2_5;
sbit at 0xA6 P2_6;
sbit at 0xA7 P2_7;
/* IEN0 */
sbit at 0xA8 EX0;
sbit at 0xA9 ET0;
sbit at 0xAA EX1;
sbit at 0xAB ET1;
sbit at 0xAC ES;
sbit at 0xAF EA;
/* IEN1 */
sbit at 0xe8 EI2C;
sbit at 0xe9 EKBI;
sbit at 0xea EC;
sbit at 0xeb ESPI;
sbit at 0xec ECCU;
sbit at 0xee EST;
sbit at 0xef EADEE;
/* P3 */
sbit at 0xB0 P3_0;
sbit at 0xB1 P3_1;
sbit at 0xB2 P3_2;
sbit at 0xB3 P3_3;
sbit at 0xB4 P3_4;
sbit at 0xB5 P3_5;
sbit at 0xB6 P3_6;
sbit at 0xB7 P3_7;
sbit at 0xB0 RXD;
sbit at 0xB1 TXD;
sbit at 0xB2 INT0;
sbit at 0xB3 INT1;
sbit at 0xB4 T0;
sbit at 0xB5 T1;
sbit at 0xB6 WR;
sbit at 0xB7 RD;
/* IP0 */
sbit at 0xB8 PX0;
sbit at 0xB9 PT0;
sbit at 0xBA PX1;
sbit at 0xBB PT1;
sbit at 0xBC PS ;
/* IP1 */
sbit at 0xf8 PI2C;
sbit at 0xf9 PKBI;
sbit at 0xfa PC;
sbit at 0xfb PSPI;
sbit at 0xfc PCCU;
sbit at 0xfe PST;
sbit at 0xff PADEE;
/* PSW */
sbit at 0xD0 P;
sbit at 0xD1 F1;
sbit at 0xD2 OV;
sbit at 0xD3 RS0;
sbit at 0xD4 RS1;
sbit at 0xD5 F0;
sbit at 0xD6 AC;
sbit at 0xD7 CY;
/* generic pin definitions */
#define PIN0 0x01
#define PIN1 0x02
#define PIN2 0x04
#define PIN3 0x08
#define PIN4 0x10
#define PIN5 0x20
#define PIN6 0x40
#define PIN7 0x80
/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
#define IDL 0x01
#define PD 0x02
#define GF0 0x04
#define GF1 0x08
#define SMOD0 0x40
#define SMOD1 0x80
/* TMOD bits */
#define T0_M0 0x01
#define T0_M1 0x02
#define T0_CT 0x04
#define T0_GATE 0x08
#define T1_M0 0x10
#define T1_M1 0x20
#define T1_CT 0x40
#define T1_GATE 0x80
#define T0_MASK 0x0F
#define T1_MASK 0xF0
/* BRGCON bits */
#define BRGEN 0x01
#define SBRGS 0x02
/* Interrupt numbers: address = (number * 8) + 3 */
#define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
#define TF0_VECTOR 1 /* 0x0b timer 0 */
#define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
#define TF1_VECTOR 3 /* 0x1b timer 1 */
#define SI0_VECTOR 4 /* 0x23 serial port 0 */
#define BOF_VECTOR 5 /* 0x2b Brown out detector */
#define I2C_VECTOR 6 /* 0x33 I2C interrupt */
#define KBI_VECTOR 7 /* 0x3b keyboard interrupt */
#define CMF_VECTOR 8 /* 0x43 comaprators 1 & 2 interrurpt */
#define SPI_VECTOR 9 /* 0x4b SPI interrupt */
#define RTC_VECTOR 10 /* 0x53 watchdog timer & real time clock */
#define CCU_VECTOR 11 /* 0x5b Capture & Compare interrupt */
#define STC_VECTOR 13 /* 0x6b serial port tx interrrupt */
#define EADEE_VECTOR 14 /* 0x73 ADC data eeprom write complete
interrupt */
#endif
*********************cut*above*here*********************************
Regards,
Rod Boyce.
--- In l..., "phlpcmicro"
wrote:
>
> Hi All,
>
> SDCC Is free open source (command line) Small Device C Complier which
> can compile 80c51 code (including Philips LPC900 series).
>
> Available here http://sdcc.sourceforge.net/
>
> An IDE (integrated development enviroment) Including SDCC is available
> here. http://www.opcube.com/home.html/
>
> In an attempt not to re-invent the wheel.
>
> I am looking for SDCC LPC900 header files for the P89LPC935 and
P89LPC938.
>
> If some one has already created them and willing to share them... that
> would be great... load them on this Yahoo group.
> Thanks in advance (use downloads at own risk)
>
> Joe
>