Hello again,

thanks for the answers so long. But my problem/question is still valid.

The databook of the LPC23xx says that the i2c interfaces can work as
master, slave or master/slave. And the only difference between i2c0
and i2c1 / i2c2 are the pin-configurations.
Also there is mentioned that only i2c0 can be powered down without
disturbing the bus.

Is this the only thing the other two i2c interfaces don't comply to
the i2c specification?
Can i use i2c1 and i2c2 in a multi master configuration (Clock
stretching problems, ...)? Has anyone tested this yet?

Greetings, Timo

An Engineer's Guide to the LPC2100 Series

> Can i use i2c1 and i2c2 in a multi master configuration (Clock
> stretching problems, ...)? Has anyone tested this yet?
>
> Greetings, Timo
>

At first glance, I assumed the lack of open drain outputs meant that
the pins couldn't float as would be required for multi-master or clock
stretching. But that isn't true. They could still tri-state without
being open drain. There is an important distinction between tri-state
and open drain.

So, off to the Datasheet and section 7.18.1 Features where it mentions
multi-master and multi-master arbitration without limiting it to I2C0.

NXP is fairly clear when they state that the pin design only limits
powering off of individual devices.

I haven't tried these parts but I would bet they work just fine (other
than power off). If they couldn't float those pins, how could the
ACK/NACK ever work?

Richard

> -----Original Message-----
> From: l...
> [mailto:l...] On Behalf Of David Hawkins
> Sent: Friday, 21 December 2007 6:05 AM
> To: l...
> Subject: Re: [lpc2000] Re: LPC23xx i2c-interface 1 and 2
>
> >
> > I don't see how 'clock stretching' by a slave can work if
> the master
> > is controlling SCL with an active device. It certainly
> won't work on
> > multi-master buses.
> >
> > This is a really bad idea... There must be a better way to
> design the
> > pin so that it can have open drain or active pull-up depending on
> > function.
>
> A tri-state pin can be used as an open-drain driver.

A tri state pin would still need the device to be powered to avoid a
clamp to VCC (=GND when no supply). The IIC spec calls for continued
operation of the IIC bus even when devices are powered down. If it was
a bus-master *only* usage (which is typically the case) then the
working-when-off requirement wouldn't really be required. So it all
depends if you want to sell your device as properly IIC compliant or
not. Phillips, inventers of the IIC bus, are likely to wish to continue
doing this.

> That of course assumes a bit-banged I2C interface. But, just
> thought I'd mention it.

Yes you can still do that, but it still leaves those 2 open drain pins
on the chip to handle anyway.
Perhaps if the manual specified the IIC pins as either IIC, or
recommended input-only/open drain instead of pretending they were normal
port pins it might save some confusion.

Cheers,
Bruce

>
> I don't see how 'clock stretching' by a slave can work if the master
> is controlling SCL with an active device. It certainly won't work on
> multi-master buses.
>
> This is a really bad idea... There must be a better way to design the
> pin so that it can have open drain or active pull-up depending on
> function.

A tri-state pin can be used as an open-drain driver.

I'll quite often use a TinyLogic tri-state buffer, tie my
I/O control to the OE pin, and the input to GND. Toggling
the I/O pin then enables the buffer to drive to GND,
or tri-states it.

I'm sure you could do the same with an LPC GPIO pin. Write 0
for the pin value, and then use the output enable control
as the drive-low or tri-state, or equivalently change the
pin direction from input (tri-state) to output.

That of course assumes a bit-banged I2C interface. But, just
thought I'd mention it.

Cheers,
Dave

--- In l..., "t.herbi" wrote:
>
> Hello,
>
> i read through the databooks of the lpc23xx devices and found that the
> i2c interfaces 1 and 2 have no open drain pins.
>
> I need all three i2c's and want to use them in master or slave mode.
> Has anyone experienced problems with this interfaces in master or
> slave mode or do they work without problems?
>
> Thanks in advance,
> Timo
>

I don't see how 'clock stretching' by a slave can work if the master
is controlling SCL with an active device. It certainly won't work on
multi-master buses.

This is a really bad idea... There must be a better way to design the
pin so that it can have open drain or active pull-up depending on
function.

Richard

--- In l..., "t.herbi" wrote:
>
> Hello,
>
> i read through the databooks of the lpc23xx devices and found that the
> i2c interfaces 1 and 2 have no open drain pins.
>
> I need all three i2c's and want to use them in master or slave mode.
> Has anyone experienced problems with this interfaces in master or
> slave mode or do they work without problems?
>
> Thanks in advance,
> Timo
>
Hi Timo,

the real open drain inputs are needed if there is a possibility that
the LPC23xx is powered off while the I2C bus is still active. In this
case the LPC23xx non-open drain inputs would most likely tie the bus
to one state. A real open drain would have no impact even when power off.

Bob

Hello,

i read through the databooks of the lpc23xx devices and found that the
i2c interfaces 1 and 2 have no open drain pins.

I need all three i2c's and want to use them in master or slave mode.
Has anyone experienced problems with this interfaces in master or
slave mode or do they work without problems?

Thanks in advance,
Timo