In article <1118553243.761323.196020@g43g2000cwa.googlegroups.com>,
methi <gmethi@gmail.com> wrote:
>Hi,
>Does anybody have any idea about bit banging using SPI interface for
>microcontrollers....esp the 8051...

Go to my page below.
Select the subject "flash programming ..."

>
>Thank you,
>Methi
>


--
-- 
Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS
Economic growth -- like all pyramid schemes -- ultimately falters.
albert@spenarnc.xs4all.nl http://home.hccnet.nl/a.w.m.van.der.horst

Hi Jim,

Whats happening is that its sending the right data for the first 16
clock cycles...

Then its not stopping...

It send all 0's


Again the right data...


So somehow the spi0dat reg is receiving the info repeatedly....

I have tried using delays between the bytes


I have also tried with just one byte for 8 clock cycles...


Same error...

It is due to SW....but i dont see wats wrong with the SW....


thanks,
Methi
Jim Granville wrote:
> methi wrote:
> > Its 16 clock pulses
> >
> >
> > Wrong data in the sense...
> >
> > Every alternate bit is reversed
>
>   Wow - It is very hard to imagine a failure mode that would do that.
> Check the device errata, but it would be _very_ hard to
> do this by accident in silicon!
>   Suspect operator error - what patterns did you use ?
>
> > And it doesnt stop with 16 clock cycles..
> >
> >
> > It generates another 16 clock cycles with all logic '0's.
>
> anything inconsistent like this screams SW oops, not HW.
> If you see correct length data, and clocks, that suggests the
> port and SFR setups are OK,
>
> You should connect MOSI to MISO, and read back single bytes, with
> a rolling test pattern. First use a SW delay to space the Bytes, then
> use the SPIF or ==, and check it works the same.
> 
> -jg

methi wrote:
> Its 16 clock pulses
> 
> 
> Wrong data in the sense...
> 
> Every alternate bit is reversed

  Wow - It is very hard to imagine a failure mode that would do that.
Check the device errata, but it would be _very_ hard to
do this by accident in silicon!
  Suspect operator error - what patterns did you use ?

> And it doesnt stop with 16 clock cycles..
> 
> 
> It generates another 16 clock cycles with all logic '0's.

anything inconsistent like this screams SW oops, not HW.
If you see correct length data, and clocks, that suggests the
port and SFR setups are OK,

You should connect MOSI to MISO, and read back single bytes, with
a rolling test pattern. First use a SW delay to space the Bytes, then
use the SPIF or ==, and check it works the same.

-jg

Since this is not working.....

I tried the bit banging method...where I have disabled the SPI by
moving data

mov    spi0cn,#002h

This disables the SPI on the chip...

And then I configured the Port 0 pins as follows:

mosi    bit    p0.4
miso    bit    p0.3
sck     bit    p0.2

And then in my program,I am calling the foll.subroutine:

fpga_talk:
 clr      fpga_cs_1
 mov      a,h5
 mov      r7,#008h
 rlc      a
 spi_loop:
 mov      mosi,c
 setb     sck
 mov      c,miso
 rlc      a
 clr      sck
 jmp      spi_loop
 djnz     r7,spi_loop
 mov      r7,a
 setb     fpga_cs_1
 ret


this doesnt seem to be working either...

What other registers should I modify in order to make this work

My port0 output config register is as follows:

mov     p0mdout,#015h

plz help...

thanku,
Methi




methi wrote:
> Its 16 clock pulses
>
>
> Wrong data in the sense...
>
> Every alternate bit is reversed
>
> And it doesnt stop with 16 clock cycles..
>
>
> It generates another 16 clock cycles with all logic '0''s.
>
> Thank you,
> Methi
>
> Jim Granville wrote:
> > methi wrote:
> > > Hello,
> > >
> > > I actually tried using the SPI interface in the micro itself..But I am
> > > not receiving the right data on the MOSI line...The SCK is fine...its
> > > 110.6khz.....
> >
> > and how many clock pulses ?
> >
> > > My slave which is an FPGA takes in the serial data and converts it into
> > > parallel...The FPGA is working fine..
> > >
> > > I have initialized my SPI registers, port 0...etc..
> > >
> > > I am right now sending two bytes of data....one following the other to
> > > the slave..
> > >
> > > When I probe my MOSI line, I see the wrong data being sent to the
> > > FPGA..
> >
> > 'Wrong' meaning what ? - no data at all, or reversed bit data, or wrong
> > baud rate, or data that is mangled by sending the second byte too soon...
> >
> >   A very simple 100% spin test for SPI, is to wire an external inverter
> > MOSI/MISO, and confirm after each completion, that RX data is inverted TX.
> > 
> > 
> > -jg

Its 16 clock pulses


Wrong data in the sense...

Every alternate bit is reversed

And it doesnt stop with 16 clock cycles..


It generates another 16 clock cycles with all logic '0''s.

Thank you,
Methi

Jim Granville wrote:
> methi wrote:
> > Hello,
> >
> > I actually tried using the SPI interface in the micro itself..But I am
> > not receiving the right data on the MOSI line...The SCK is fine...its
> > 110.6khz.....
>
> and how many clock pulses ?
>
> > My slave which is an FPGA takes in the serial data and converts it into
> > parallel...The FPGA is working fine..
> >
> > I have initialized my SPI registers, port 0...etc..
> >
> > I am right now sending two bytes of data....one following the other to
> > the slave..
> >
> > When I probe my MOSI line, I see the wrong data being sent to the
> > FPGA..
>
> 'Wrong' meaning what ? - no data at all, or reversed bit data, or wrong
> baud rate, or data that is mangled by sending the second byte too soon...
>
>   A very simple 100% spin test for SPI, is to wire an external inverter
> MOSI/MISO, and confirm after each completion, that RX data is inverted TX.
> 
> 
> -jg

methi wrote:
> Hello,
> 
> I actually tried using the SPI interface in the micro itself..But I am
> not receiving the right data on the MOSI line...The SCK is fine...its
> 110.6khz.....

and how many clock pulses ?

> My slave which is an FPGA takes in the serial data and converts it into
> parallel...The FPGA is working fine..
> 
> I have initialized my SPI registers, port 0...etc..
> 
> I am right now sending two bytes of data....one following the other to
> the slave..
> 
> When I probe my MOSI line, I see the wrong data being sent to the
> FPGA..

'Wrong' meaning what ? - no data at all, or reversed bit data, or wrong 
baud rate, or data that is mangled by sending the second byte too soon...

  A very simple 100% spin test for SPI, is to wire an external inverter 
MOSI/MISO, and confirm after each completion, that RX data is inverted TX.


-jg

On 13 Jun 2005 09:08:43 -0700, methi wrote:

> The XBR0 register is initialized with the value:
> 
> XBR0    =  0x0F;             // skip SPI pins in XBAR
> 
> Should I be doing the same?
Yes it is absolutely critical that you follow the XBAR priority
requirements to the letter. Otherwise it will definitely not work. I don't
have the F022 data sheet here, but read that section carefully and make
sure you have assigned all of the port bits' special functions properly.


Bob

Hi,

I have tried sending data from 8051 to the fpga using the Bit banging
method as follows:

This is a subroutine that I am calling everytime my H5 value changes:

fpga_talk:
 clr      fpga_cs_1
 mov      a,h5
 mov      r7,#008h
 rlc      a
 spi_loop:
 mov      p0.4,c
 setb     p0.2
 mov      c,p0.3
 rlc      a
 clr      p0.2
 djnz     r7,spi_loop
 mov      r7,a
 setb     fpga_cs_1
 ret


I have also disabled the on chip SPI interface.

Still I dont seem to be seeing any clock at the sck line at p0.2

I dont know what I am doing wrong...

plz help...

thank you,
Methi

methi wrote:
> I also have another question
>
> The SPIF bit is set to logic 1 everytime a data transfer is complete..
>
> When interrupts are enabled, setting this bit causes the CPU to vector
> to the SPI0 ISR.
>
> I dont have any SPI0 ISR written...so what does this mean?
> 
> 
> Thank you,
> Methi

I also have another question

The SPIF bit is set to logic 1 everytime a data transfer is complete..

When interrupts are enabled, setting this bit causes the CPU to vector
to the SPI0 ISR.

I dont have any SPI0 ISR written...so what does this mean?


Thank you,
Methi

Hi,

I have not connected the NSS line write now...

But you are saying that I should tie it high rite?

Thank you,
Methi
Tauno Voipio wrote:
> methi wrote:
> > Hi Tim,
> >
> > I am using Cygnal's C8051F022 which has an SPI interface.
> >
> > I am using a three-wire transfer mode with the lines MOSI,SCK and MISO.
> >
> > My SPI slave is an FPGA.
> >
>
> You need to control the slave select (SS-) line to
> synchronize the slave before the transfer.
> 
> -- 
> 
> Tauno Voipio
> tauno voipio (at) iki fi