Reply by "sub...@aeolusdevelopment.com"●March 26, 20082008-03-26
shwouchk Wrote >--- In l..., Robert Adsett
wrote:
>>
>> At 01:14 AM 3/25/2008 +0000, shwouchk wrote:
>> >I am writing code for handling uart right now, and I became concerned
>> >with the size of the Tx fifo and of overrunning it.
> >
> >What would you recommend for me to do to solve this problem?
>
> There really only is one way. When you get a THRE stuff up to 16 chars
> into the FIFO. The wait for the next interrupt and do it again. For
> continuous transmission that cuts your interrupt overhead by a factor of
> 16, less for more intermittent transmit but it can still be substantial. I > wouldn't call it highly inefficient but a DMA
setup can take less overhead.
>As I thought..
>Thanks!
>One more thing - What do you mean by a DMA setup?
Some microcontrollers have a DMA (or pseudo-DMA) available response for
servicing interrupts. HW intercepts the interrupt and transfers a byte
from memory to the UART. This completely avoids the need to do an
interrupt context switch since the CPU core isn't involved and reduces
the
overhead to the memory access. The overhead goes down substantially, if
the DMA can use memory cycles the microcontroller isn't the overhead can
actually go to zero. Not available for the UART on any LPC as far as I
know.
At 01:14 AM 3/25/2008 +0000, shwouchk wrote: >Hi,
>
>I am writing code for handling uart right now, and I became concerned
>with the size of the Tx fifo and of overrunning it.
>
>I thought about using the scratch register to count how many chars
>were sent and each time it gets to 16 to wait for a THRE interrupt to
>clear it. I think this method would be highly inefficient in terms of
>uart transmission rates.
>
>What would you recommend for me to do to solve this problem?
There really only is one way. When you get a THRE stuff up to 16 chars
into the FIFO. The wait for the next interrupt and do it again. For
continuous transmission that cuts your interrupt overhead by a factor of
16, less for more intermittent transmit but it can still be substantial. I
wouldn't call it highly inefficient but a DMA setup can take less
overhead.
Unless your baud rates are really high you will fill the FIFO before the
first character transmit anyway.
Robert
"A million lines of code costs $20m to $40m ..... a million times
the cost of the flash chips it lives in. .... Yet accounting screams
over each added penny in recurring costs, while chanting the
dual mantras 'software is free,' and 'hey, it's only a
software
change.'" Jack Ganssle in "A Million Lines of Code"
I am writing code for handling uart right now, and I became concerned
with the size of the Tx fifo and of overrunning it.
I thought about using the scratch register to count how many chars
were sent and each time it gets to 16 to wait for a THRE interrupt to
clear it. I think this method would be highly inefficient in terms of
uart transmission rates.
What would you recommend for me to do to solve this problem?
