I've seen notes elsewhere on this forum about RDRF behavior on the '7X, but none exactly describe what I'm seeing.

I'm doing non-interrupt SPI I/O in an ISR that is invoked to respond to a hardware condition. The AT91 is the SPI Master and I need to exchange three words quickly with a CPLD. That's been working for a while, but one in a while the read data was wrong. The odd part is the code wasn't pending on RDRF. It did something like

write word to SPI0
wait for TDRE = 1
read word from SPI0

To deal with occasional bad read data, I started pending on RDRF. I just changed the code to do this now:

write word to SPI0
wait for TDRE=1 and RDRF=1
read word from SPI0

The strangeness is what I see on the 'scope. Before waiting for RDRF, SPI bus cycles would occur back-to-back with an inter-word delay limited only by firmware speed. But now that I wait for RDRF, there is a 1.2uS gap between NSS cycles, a little shorter than the SPI word transfer time (16 bits, MCLKH MHz, DLYBS=5, SCBR=4).

So my question is, what is the hardware doing during this time? Is RDRF delayed for some reason, or are the received bits being shifted serially into another register? It cuts my throughput in half - 2.5us per 16b word instead of about 1.5us per word.

Any thoughts? Is this what others are seeing?

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