Hi Mohsen,
Synplify Pro is able to generate output netlist in EDIF / VHDL / Verilog.
You have to change your script of Synplify Pro for generating the VHDL
output netlist.
Otherway, you will need to have an EDIF2VHDL converter. Please contact
me, I have written a EDIF2VHDL in perl language.
Kind regards,
Laurent Gauch
www.amontec.com
yousef_p_m wrote:
> Dear Friends,
>
> I have written a verilog code for a module. I have synthesized it with
> Synplify Pro for a Virtex II Pro chip and it has given me an edif
> netlist file. Now I want to use this synthesized edif file as a
> peripheral and import it to my system via import peripheral wizard in
> XPS. but it seems we are not allowed to import an edf file without a
> top level HDL file.
> could you please tell me how do I can import a edf file to a XPS system?
>
> Regards,
> Mohsen.
>
>
>
> This message was sent using the comp.arch.embedded web interface on
> www.EmbeddedRelated.com
Reply by yousef_p_m●July 19, 20052005-07-19
Dear Friends,
I have written a verilog code for a module. I have synthesized it with
Synplify Pro for a Virtex II Pro chip and it has given me an edif
netlist file. Now I want to use this synthesized edif file as a
peripheral and import it to my system via import peripheral wizard in
XPS. but it seems we are not allowed to import an edf file without a
top level HDL file.
could you please tell me how do I can import a edf file to a XPS system?
Regards,
Mohsen.
This message was sent using the comp.arch.embedded web interface o
www.EmbeddedRelated.com