It's only on the label but not the actual part # on the device? I just want to make sure there are funtionality issue if using this device in replace of V2p that does not have this suffix?

Rdgs,

David M. Gregory
SG Industries
I-Phone: 978-289-2424

On Apr 10, 2010, at 6:59 PM, "brimdavis" > wrote:

>
> Can anyone explain to me what the "R01" calls out on the
> Xilinx Virtex Pro, XC2VP70-6FF1517CR01, in the suffix ?
>

I'd guess that to be a die revision or stepping indication.

Is that actually what is marked on the package, or just a
part number/order code ?

Sometimes for ordering purposes, you have to add a code
to the end of the part number to get a particular stepping,
IIRC usually called an SCD code.

I'd check the V2Pro datasheet, Errata, and Answer Records
for a more definitive answer- any die revision info usually
ends up in at least one of those places.

E.g., some of the V2Pro revision markings are detailed in
Answer Record 17244, but with a 3 digit alpha code after the
package type or a 4 digit SCD code after the temp/speed grade,
as described in the 'traceability' section of the following:

http://www.xilinx.com/support/answers/17244.htm

Part marking info from the packaging guide:
UG112 3.5, Table 1-2, page 15:
"
" 1st Line Device type.
"
" 2nd Line Package type and pin count, circuit design revision,
" the location code for the wafer fab, the geometry code,
" and date code
"

Checking the Avnet website, that part is listed as:
" XC2VP70-6FF1517CR01
" REVISION CONTROL FOR PCN R01

But a quick look for a "Process Change Notice" under the
"Customer Notices" section of the V2Pro documentation page
didn't turn up anything obvious:
http://www.xilinx.com/support/documentation/virtex-ii_pro.htm

Brian





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>
> Can anyone explain to me what the "R01" calls out on the
> Xilinx Virtex Pro, XC2VP70-6FF1517CR01, in the suffix ?
>

I'd guess that to be a die revision or stepping indication.

Is that actually what is marked on the package, or just a
part number/order code ?

Sometimes for ordering purposes, you have to add a code
to the end of the part number to get a particular stepping,
IIRC usually called an SCD code.

I'd check the V2Pro datasheet, Errata, and Answer Records
for a more definitive answer- any die revision info usually
ends up in at least one of those places.

E.g., some of the V2Pro revision markings are detailed in
Answer Record 17244, but with a 3 digit alpha code after the
package type or a 4 digit SCD code after the temp/speed grade,
as described in the 'traceability' section of the following:

http://www.xilinx.com/support/answers/17244.htm
Part marking info from the packaging guide:
UG112 3.5, Table 1-2, page 15:
"
" 1st Line Device type.
"
" 2nd Line Package type and pin count, circuit design revision,
" the location code for the wafer fab, the geometry code,
" and date code
"
Checking the Avnet website, that part is listed as:
" XC2VP70-6FF1517CR01
" REVISION CONTROL FOR PCN R01

But a quick look for a "Process Change Notice" under the
"Customer Notices" section of the V2Pro documentation page
didn't turn up anything obvious:
http://www.xilinx.com/support/documentation/virtex-ii_pro.htm
Brian



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The RoHS version would have a "G" in the part # :

.......6FFG1517C

?

David M. Gregory
SG Industries
978-922-4299
www.sgidirect.com

Where the Quality istm
________________________________
From: f... [mailto:f...] On Behalf Of Alex Perez
Sent: Wednesday, April 07, 2010 11:38 PM
To: f...
Subject: Re: [fpga-cpu] Virtex Pro - R01 in suffix
Importance: High

On Apr 7, 2010, at 11:28 AM, David Gregory wrote:

> Can anyone explain to me what the "R01" calls out on the Xilinx Virtex Pro, XC2VP70-6FF1517CR01, in the suffix ?
>
A guess would be "RoHS Rev 1"
>
> Any Help is appreciated.
>
> Thank you,
>
> David M. Gregory
> SG Industries
> 978-922-4299
> www.sgidirect.com Where the Quality istm
> ________________________________
> From: f... [mailto:f...] On Behalf Of ruchi_rastogi25
> Sent: Sunday, August 02, 2009 4:01 AM
> To: f...
> Subject: [fpga-cpu] Implementation of LRU algo in verilog
>
> Hi all,
> I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware.
> Thanks,
> Ruchi
>
>







To post a message, send it to: f...
To unsubscribe, send a blank message to: f... Start a New Thread

On Apr 7, 2010, at 11:28 AM, David Gregory wrote:

> Can anyone explain to me what the "R01" calls out on the Xilinx Virtex Pro, XC2VP70-6FF1517CR01, in the suffix ?
>
A guess would be "RoHS Rev 1"
>
> Any Help is appreciated.
>
> Thank you,
>
> David M. Gregory
> SG Industries
> 978-922-4299
> www.sgidirect.com Where the Quality istm
> ________________________________
> From: f... [mailto:f...] On Behalf Of ruchi_rastogi25
> Sent: Sunday, August 02, 2009 4:01 AM
> To: f...
> Subject: [fpga-cpu] Implementation of LRU algo in verilog
>
> Hi all,
> I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware.
> Thanks,
> Ruchi
>
>





To post a message, send it to: f...
To unsubscribe, send a blank message to: f... Start a New Thread

Can anyone explain to me what the "R01" calls out on the Xilinx Virtex Pro, XC2VP70-6FF1517CR01, in the suffix ?

Any Help is appreciated.

Thank you,

David M. Gregory
SG Industries
978-922-4299
www.sgidirect.com

Where the Quality istm
________________________________
From: f... [mailto:f...] On Behalf Of ruchi_rastogi25
Sent: Sunday, August 02, 2009 4:01 AM
To: f...
Subject: [fpga-cpu] Implementation of LRU algo in verilog

Hi all,
I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware.
Thanks,
Ruchi





To post a message, send it to: f...
To unsubscribe, send a blank message to: f... Start a New Thread

Hi Ruchi,

On Sun, 2009-08-02 at 08:00 +0000, ruchi_rastogi25 wrote:

> I am designing a cache memory in verilog. I am facing problem in
> desiging LRU unit for set associative cache. Can anybody tell me what
> is the optimal way of implementating LRU(Least Recently Used)algo in
> Hardware.

in your application, is it absolutely necessary to implement
an exact LRU replacement scheme? Then the associativity of your
cache should be small. Otherwise you could approximate LRU, or
even use random replacement. I cite from Patterson & Hennessy:

"In practice, LRU is too costly to implement for hierarchies
with more than a small degree of associativity (two to four,
typically). [...] Even for four-way set associativity, LRU is
often approximated - for example, by keeping track of which of
a pair of blocks is LRU (which requires 1 bit), and then tracking
which block in each pair is LRU (which requires 1 bit per pair).
[...] Random replacement is simple to build in hardware, and
for a two-way set-associative cache, random replacement has
a miss rate about 1.1 times higher than LRU replacement. [...]
In fact, random replacement is sometimes better than simple LRU
approximations that can be easily implemented in hardware."

Hellwig



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Hi all,
I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware.
Thanks,
Ruchi



To post a message, send it to: f...
To unsubscribe, send a blank message to: f... Start a New Thread