Is there any published documentation which contains this information
(e.g.: that VPB operations are 3 clocks)?
--- In , "philips_apps" <philips_apps@y...>
> Here is an explanation of the I/O toggle speed that is observed in
> these devices.
> The I/O speed has a maximum at ~3.7 Mhz because of several reasons,
> none specific to our parts. It is caused by interactions between
> ARM pipeline, the VPB bus, the ARM AHB wrapper (interface between
> ARM7TDMI-S core and the AHB bus), and the instruction timing
> For the minimum 3-instruction loop below, a Store (Write to I/O
> followed by another Store (toggle the I/O pin) and a Branch back to
> the first Store, the timing is as follows (Fe for Fetch, De for
> Decode, En for execution clock n):
> STR: Fe-De-E1-E1-E2-E2-E2-E2-E2
> STR: Fe-De----------------------------E1-E1-E2-E2-E2-E2
> B: Fe-----------------------------De-----------------
> And so on...
> An STR to VPB space takes 8 clocks because the last 2 phases (STR
> a 4 phase instruction) are Non-Sequential (NS) accesses and the AHB
> wrapper adds one wait state for every NS access. This means the 3rd
> phase of the instruction takes 2 clocks, and the fourth phase takes
> because of the wait state and the VPB operations being 3 clocks.
> The second STR can be fetched and Decoded in the pipeline but will
> then stall because the execution pipeline stage is busy (the first
> Store has not completed yet). The Branch instruction can also be
> fetched in the Decode slot of the second STR but it will then stall
> because the Decode stall is occupied by the second STR.
> After the first STR completes, the second STR will start its
> execution phase and finally will allow the Branch instruction
> also has one NS phase) to proceed.
> End result: This takes 16 clocks (266.7 ns at 60 MHz with VPB clock
> set to 1) with a duty cycle of 6:10 . > Code:
> str r2, [r7, #0]
> str r2, [r6, #0]
> b .loop