[reposting since original posting seem to be gone]

<ryan.pinto79@gmail.com> wrote in message
news:1123858848.239594.54830@z14g2000cwz.googlegroups.com...
> Hi, I need to stream audio data and control info I2C out of my PC into
> some external hardware and was thinking of using a FIFO to deal with
> the different clock boundaries.
>
> I was wondering if anyone had some startup verilog code on FIFOs, I am
> using a Xilinx FPGA

You may want to look at Xilinx application note 175, together with the zip
archive containing the HDL code. It has both synchronous and asynchronous
FIFOs ready to go.

DJ
--

<ryan.pinto79@gmail.com> wrote in message
news:1123858848.239594.54830@z14g2000cwz.googlegroups.com...
> Hi, I need to stream audio data and control info I2C out of my PC into
> some external hardware and was thinking of using a FIFO to deal with
> the different clock boundaries.
>
> I was wondering if anyone had some startup verilog code on FIFOs, I am
> using a Xilinx FPGA

You may want to look at Xilinx application note 175, together with the zip
archive containing the HDL code. It has both synchronous and asynchronous
FIFOs ready to go.

DJ
--

ryan.pinto79@gmail.com wrote:
> Hi, I need to stream audio data and control info I2C out of my PC into
> some external hardware and was thinking of using a FIFO to deal with
> the different clock boundaries.
> 
> I was wondering if anyone had some startup verilog code on FIFOs, I am
> using a Xilinx FPGA
> 

I agree with "GMM50", don't waste your time writing your own FIFO. Pick 
one from the Xilinx library. They should have ready-made FIFOs 
available, if not then switch to Altera.

-JV

I've done just that using ALtera's tools except I used the graphical
design as the input.  So I placed a fifo set it width and depth.  Then
wraped controling logid arround it.

I then had the tools generate VHDL output.

I'm still using the graphical as the master but could switch when
necessary.

George

Hi, I need to stream audio data and control info I2C out of my PC into
some external hardware and was thinking of using a FIFO to deal with
the different clock boundaries.

I was wondering if anyone had some startup verilog code on FIFOs, I am
using a Xilinx FPGA

Thanks

Ryan
(ryan.pinto79@gmail.com)