jtyler wrote:
> >Tauno thanks for getting back with me.
> I guess i dont know what pin is the clock power line.  Is it the core
> voltage ?

Not sure if it is from VDDCORE or VDDOSC.  You need to hook up both
anyway.  In standby mode, the processor draw 3mA from VDDCORE.

> Am I screwing up by not having 32 bit dynamic memory ?  I really dont want
> to bog the system down that much.
> Will I be glad in the end that i installed the dynamic memory ?

If you need more memory, SDRAM would be cheaper.

>
> I dont see where the address boundaries get set for the CS0-CS7 in the
> SMC.
> Gee Whiz I really need to understand the chip selects, and it looked to me
> that the chip select boundaries were hardwired for 64Mbyte pages ?

Yes, all CS are 64M pages.  That why you need the MMU.

>
> COuld You enlighten me on this, I am new to this processor.
>
> Thanks Alot,
> John
>
>
> >Tauno Voipio wrote:
> >> jtyler wrote:
> >> > Hi All,
> >> > I have a few questions on implementation:
> >> > P.S. I have read the manual closely.
> >> > 1. How does the real time clock keep time during power cycles ?
> >
> >You need to battery power the clock power line.
> >
> >> > 2.I want to run my code in flash, i think these days it is fast
> enough, i
> >> > know it is only 16 bit and must use thumb mode on compiler.  What
> other
> >> > problems will i not like ?
> >>
> >> The memory width and the instruction width are separate.
> >> The bus interface is smart enough to use two 16 bit
> >> cycles for a single 32 bit instruction fetch. Besides,
> >> the processor always wakes up in 32 bit mode.
> >
> >Or 1 bit mode if you have data flash.
> >
> >
> >> > 3. My RAM memory will be SRAM which again is only 16 bit and must be
> >> > battery backed to retain state of machine during power cycles, which
> is
> >> > what i need .
> >
> >What wrong with writing data to flash, upon power down?
> >
> >>
>
> >> You have also to protect the RAM control lines against
> >> glitches at power up and power down, to prevent corruption
> >> of the stored contents.
> >
> >And all processor states and registers.
> >
> >
>
>
>
> This message was sent using the comp.arch.embedded web interface on
> www.EmbeddedRelated.com

>Tauno thanks for getting back with me. 
I guess i dont know what pin is the clock power line.  Is it the cor
voltage ?

Ok, on the state of the machine during power cycle.
I just need to remember some user memory that is updated alot, so flas
wouldnt work, thus the SRAM.

Am I screwing up by not having 32 bit dynamic memory ?  I really dont wan
to bog the system down that much. 
Will I be glad in the end that i installed the dynamic memory ?

I dont see where the address boundaries get set for the CS0-CS7 in th
SMC.
Gee Whiz I really need to understand the chip selects, and it looked to m
that the chip select boundaries were hardwired for 64Mbyte pages ?

COuld You enlighten me on this, I am new to this processor.

Thanks Alot,
John 


>Tauno Voipio wrote:
>> jtyler wrote:
>> > Hi All,
>> > I have a few questions on implementation:
>> > P.S. I have read the manual closely.
>> > 1. How does the real time clock keep time during power cycles ?
>
>You need to battery power the clock power line.
>
>> > 2.I want to run my code in flash, i think these days it is fas
enough, i
>> > know it is only 16 bit and must use thumb mode on compiler.  Wha
other
>> > problems will i not like ?
>>
>> The memory width and the instruction width are separate.
>> The bus interface is smart enough to use two 16 bit
>> cycles for a single 32 bit instruction fetch. Besides,
>> the processor always wakes up in 32 bit mode.
>
>Or 1 bit mode if you have data flash.
>
>
>> > 3. My RAM memory will be SRAM which again is only 16 bit and must be
>> > battery backed to retain state of machine during power cycles, whic
is
>> > what i need .
>
>What wrong with writing data to flash, upon power down?
>
>>

>> You have also to protect the RAM control lines against
>> glitches at power up and power down, to prevent corruption
>> of the stored contents.
>
>And all processor states and registers.
>
>


		
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Tauno Voipio wrote:
> jtyler wrote:
> > Hi All,
> > I have a few questions on implementation:
> > P.S. I have read the manual closely.
> > 1. How does the real time clock keep time during power cycles ?

You need to battery power the clock power line.

> > 2.I want to run my code in flash, i think these days it is fast enough, i
> > know it is only 16 bit and must use thumb mode on compiler.  What other
> > problems will i not like ?
>
> The memory width and the instruction width are separate.
> The bus interface is smart enough to use two 16 bit
> cycles for a single 32 bit instruction fetch. Besides,
> the processor always wakes up in 32 bit mode.

Or 1 bit mode if you have data flash.


> > 3. My RAM memory will be SRAM which again is only 16 bit and must be
> > battery backed to retain state of machine during power cycles, which is
> > what i need .

What wrong with writing data to flash, upon power down?

>
> You have also to protect the RAM control lines against
> glitches at power up and power down, to prevent corruption
> of the stored contents.

And all processor states and registers.

jtyler wrote:
> Hi All,
> I have a few questions on implementation:
> P.S. I have read the manual closely.
> 1. How does the real time clock keep time during power cycles ?
> 2.I want to run my code in flash, i think these days it is fast enough, i
> know it is only 16 bit and must use thumb mode on compiler.  What other
> problems will i not like ?

The memory width and the instruction width are separate.
The bus interface is smart enough to use two 16 bit
cycles for a single 32 bit instruction fetch. Besides,
the processor always wakes up in 32 bit mode.

The narrow memory slows down the instruction feed
to the processor, so baout half of the nominal speed
can be expected.

> 3. My RAM memory will be SRAM which again is only 16 bit and must be
> battery backed to retain state of machine during power cycles, which is
> what i need .

You have also to protect the RAM control lines against
glitches at power up and power down, to prevent corruption
of the stored contents.

> 4. The SRAM controller in the chip does 64MByte chip selects if my flash
> start at 0 CS0 and for 8Mbytes where does my SRAM start if on CS1 ?
> These are probably dumb questions, but, i am not that smart!

It depends entirely on what you write into the chip select
registers at startup. Read the EBI manual.

Please understand that on the AT91RM9200 you have two sets
of addresses: logical, seen by the code and physical, seen
by the bus hardware. The memory mapping unit converts between
these two sets.

-- 

Tauno Voipio
tauno voipio (at) iki fi

Hi All,
I have a few questions on implementation:
P.S. I have read the manual closely.
1. How does the real time clock keep time during power cycles ?
2.I want to run my code in flash, i think these days it is fast enough, 
know it is only 16 bit and must use thumb mode on compiler.  What othe
problems will i not like ?
3. My RAM memory will be SRAM which again is only 16 bit and must b
battery backed to retain state of machine during power cycles, which i
what i need .
4. The SRAM controller in the chip does 64MByte chip selects if my flas
start at 0 CS0 and for 8Mbytes where does my SRAM start if on CS1 ?
These are probably dumb questions, but, i am not that smart!

Anyway any answers would be much appreciated.
THanks,
John


		
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