Hi Jim,

Sorry - which data sheet are you refering to? (re. page 28)

I have the FG4618 data sheet (SLAS508G - APRIL 2006 - REVISED OCT. 2007) and I see no such figure on page 28.

This might be my problem - since I'm running at 3.3V.

Yes, I'm aware of the load cap. specification - only I didn't know the vendor of the crystal.
(I've since changed it to a known device which requires 12.5pF load caps - but set the MSP regs. for 14pF)

No, we've never had to calculate a modulator value - and I wouldn't know where to start!? :-/

Forget about the OR'ing - this is not my code, but I've checked the regs. in the debugger.

Thanks.

Regards,
Darren
-----Original Message-----
From: m... [mailto:m...]On Behalf Of Jim Carlson
Sent: 12 March 2008 12:18
To: m...
Subject: RE: [msp430] ACLK multiplying question

I know this may not be exactly what you are after, but since I have seen
similar problems, I thought I would share what I learned. On page 28 of
MSP430xG461x data sheet is a Figure 1. To operate at 8.0 MHZ your Supply
voltage needs to be 3.6v.

Your load caps are a function of the crystal vendor you are using and the
trace layout you have for your crystal.

And lastly, although it is rather complex, did you calculate your modulator
value?

Also, you are ORing in values. Why not just set the values to what you want.

SCFQCTL |= 121; /* multiplier N */
With this statement, the value in SCFQCTL may not be 121.

Thanks,

Jim

_____

From: msp430@yahoogroups. com [mailto: msp430@yahoogroups. com] On Behalf Of
Darren Logan
Sent: Wednesday, March 12, 2008 5:50 AM
To: msp430@yahoogroups. com
Subject: [msp430] ACLK multiplying question
Importance: High

Hi all,

Please could you help me with the following:

I've been given some IAR code (and dev. board with MSP430FG4618) which
aparently multiplies the 32.768 watch
crystal on XT1 up to 8.000MHz via the FLL/DCO.

This 8.0MHz is then used as SMCLK for the RS232 UART - specifically UCA0
(pins 2.4 and 2.5).

I need a baud rate of 9600 on this, but IAR debugger is showing me framing
errors on the data coming in... even
though the data is actually correct.

Now, if I change UCA0BR0 (low byte of the baud rate registers) I can get it
to work without framing errors - but this
is only through trial & error.

It's possible my XT load cap setting is wrong - which could be causing the
errors in the baud timing, but first I need to know
whether the clock has been setup correctly or not. The clock code is below:

FLL_CTL0 |= XCAP14PF; /* configure load caps */
/* Multiply input xtal freq of 32768 Hz up to *MHz */
FLL_CTL0 |= DCOPLUS; /* DCO+ divider set, freq = xtal x D x (N +1) DCO
output is NOT divided*/
SCFI0 |= FN_4; /* DCO frequency range, 8MHz nominal */
SCFI0 |= FLLD_2; /* DCO loop divider for D = 2 freq doubling */
SCFQCTL |= 121; /* multiplier N */
/* Select the source for Main Clock (MCLCK) and Sum Main Clock (SMCLCK) */
FLL_CTL1 |= SELM0; /* Select DCOCLK (= 8 MHz) as the source for MLCK . And
its by default the source for SMCLK. */

Does this look correct to you? (to multiply 32.768 XT1 up to 8.00MHz?)

What is the actual multiplied frequency? (I make it 7929856 Hz)

Thanks in advance.

Regards,
Darren Start a New Thread

I know this may not be exactly what you are after, but since I have seen
similar problems, I thought I would share what I learned. On page 28 of
MSP430xG461x data sheet is a Figure 1. To operate at 8.0 MHZ your Supply
voltage needs to be 3.6v.

Your load caps are a function of the crystal vendor you are using and the
trace layout you have for your crystal.

And lastly, although it is rather complex, did you calculate your modulator
value?

Also, you are ORing in values. Why not just set the values to what you want.

SCFQCTL |= 121; /* multiplier N */
With this statement, the value in SCFQCTL may not be 121.

Thanks,

Jim

_____

From: m... [mailto:m...] On Behalf Of
Darren Logan
Sent: Wednesday, March 12, 2008 5:50 AM
To: m...
Subject: [msp430] ACLK multiplying question
Importance: High

Hi all,

Please could you help me with the following:

I've been given some IAR code (and dev. board with MSP430FG4618) which
aparently multiplies the 32.768 watch
crystal on XT1 up to 8.000MHz via the FLL/DCO.

This 8.0MHz is then used as SMCLK for the RS232 UART - specifically UCA0
(pins 2.4 and 2.5).

I need a baud rate of 9600 on this, but IAR debugger is showing me framing
errors on the data coming in... even
though the data is actually correct.

Now, if I change UCA0BR0 (low byte of the baud rate registers) I can get it
to work without framing errors - but this
is only through trial & error.

It's possible my XT load cap setting is wrong - which could be causing the
errors in the baud timing, but first I need to know
whether the clock has been setup correctly or not. The clock code is below:

FLL_CTL0 |= XCAP14PF; /* configure load caps */
/* Multiply input xtal freq of 32768 Hz up to *MHz */
FLL_CTL0 |= DCOPLUS; /* DCO+ divider set, freq = xtal x D x (N +1) DCO
output is NOT divided*/
SCFI0 |= FN_4; /* DCO frequency range, 8MHz nominal */
SCFI0 |= FLLD_2; /* DCO loop divider for D = 2 freq doubling */
SCFQCTL |= 121; /* multiplier N */
/* Select the source for Main Clock (MCLCK) and Sum Main Clock (SMCLCK) */
FLL_CTL1 |= SELM0; /* Select DCOCLK (= 8 MHz) as the source for MLCK . And
its by default the source for SMCLK. */

Does this look correct to you? (to multiply 32.768 XT1 up to 8.00MHz?)

What is the actual multiplied frequency? (I make it 7929856 Hz)

Thanks in advance.

Regards,
Darren Start a New Thread

Try page 30 of your version.

Thanks,

Jim

_____

From: m... [mailto:m...] On Behalf Of
Darren Logan
Sent: Wednesday, March 12, 2008 8:37 AM
To: m...
Subject: RE: [msp430] ACLK multiplying question
Importance: High

Hi Jim,

Sorry - which data sheet are you refering to? (re. page 28)

I have the FG4618 data sheet (SLAS508G - APRIL 2006 - REVISED OCT. 2007) and
I see no such figure on page 28.

This might be my problem - since I'm running at 3.3V.

Yes, I'm aware of the load cap. specification - only I didn't know the
vendor of the crystal.
(I've since changed it to a known device which requires 12.5pF load caps -
but set the MSP regs. for 14pF)

No, we've never had to calculate a modulator value - and I wouldn't know
where to start!? :-/

Forget about the OR'ing - this is not my code, but I've checked the regs. in
the debugger.

Thanks.

Regards,
Darren

-----Original Message-----
From: msp430@yahoogroups. com
[mailto:msp430@yahoogroups. com]On Behalf
Of Jim Carlson
Sent: 12 March 2008 12:18
To: msp430@yahoogroups. com
Subject: RE: [msp430] ACLK multiplying question

I know this may not be exactly what you are after, but since I have seen
similar problems, I thought I would share what I learned. On page 28 of
MSP430xG461x data sheet is a Figure 1. To operate at 8.0 MHZ your Supply
voltage needs to be 3.6v.

Your load caps are a function of the crystal vendor you are using and the
trace layout you have for your crystal.

And lastly, although it is rather complex, did you calculate your modulator
value?

Also, you are ORing in values. Why not just set the values to what you want.

SCFQCTL |= 121; /* multiplier N */
With this statement, the value in SCFQCTL may not be 121.

Thanks,

Jim

_____

From: msp430@yahoogroups. com [mailto:
msp430@yahoogroups. com] On Behalf Of
Darren Logan
Sent: Wednesday, March 12, 2008 5:50 AM
To: msp430@yahoogroups. com
Subject: [msp430] ACLK multiplying question
Importance: High

Hi all,

Please could you help me with the following:

I've been given some IAR code (and dev. board with MSP430FG4618) which
aparently multiplies the 32.768 watch
crystal on XT1 up to 8.000MHz via the FLL/DCO.

This 8.0MHz is then used as SMCLK for the RS232 UART - specifically UCA0
(pins 2.4 and 2.5).

I need a baud rate of 9600 on this, but IAR debugger is showing me framing
errors on the data coming in... even
though the data is actually correct.

Now, if I change UCA0BR0 (low byte of the baud rate registers) I can get it
to work without framing errors - but this
is only through trial & error.

It's possible my XT load cap setting is wrong - which could be causing the
errors in the baud timing, but first I need to know
whether the clock has been setup correctly or not. The clock code is below:

FLL_CTL0 |= XCAP14PF; /* configure load caps */
/* Multiply input xtal freq of 32768 Hz up to *MHz */
FLL_CTL0 |= DCOPLUS; /* DCO+ divider set, freq = xtal x D x (N +1) DCO
output is NOT divided*/
SCFI0 |= FN_4; /* DCO frequency range, 8MHz nominal */
SCFI0 |= FLLD_2; /* DCO loop divider for D = 2 freq doubling */
SCFQCTL |= 121; /* multiplier N */
/* Select the source for Main Clock (MCLCK) and Sum Main Clock (SMCLCK) */
FLL_CTL1 |= SELM0; /* Select DCOCLK (= 8 MHz) as the source for MLCK . And
its by default the source for SMCLK. */

Does this look correct to you? (to multiply 32.768 XT1 up to 8.00MHz?)

What is the actual multiplied frequency? (I make it 7929856 Hz)

Thanks in advance.

Regards,
Darren Start a New Thread

Hi all,

Please could you help me with the following:

I've been given some IAR code (and dev. board with MSP430FG4618) which aparently multiplies the 32.768 watch
crystal on XT1 up to 8.000MHz via the FLL/DCO.

This 8.0MHz is then used as SMCLK for the RS232 UART - specifically UCA0 (pins 2.4 and 2.5).

I need a baud rate of 9600 on this, but IAR debugger is showing me framing errors on the data coming in... even
though the data is actually correct.

Now, if I change UCA0BR0 (low byte of the baud rate registers) I can get it to work without framing errors - but this
is only through trial & error.

It's possible my XT load cap setting is wrong - which could be causing the errors in the baud timing, but first I need to know
whether the clock has been setup correctly or not. The clock code is below:

FLL_CTL0 |= XCAP14PF; /* configure load caps */
/* Multiply input xtal freq of 32768 Hz up to *MHz */
FLL_CTL0 |= DCOPLUS; /* DCO+ divider set, freq = xtal x D x (N +1) DCO output is NOT divided*/
SCFI0 |= FN_4; /* DCO frequency range, 8MHz nominal */
SCFI0 |= FLLD_2; /* DCO loop divider for D = 2 freq doubling */
SCFQCTL |= 121; /* multiplier N */
/* Select the source for Main Clock (MCLCK) and Sum Main Clock (SMCLCK) */
FLL_CTL1 |= SELM0; /* Select DCOCLK (= 8 MHz) as the source for MLCK . And its by default the source for SMCLK. */

Does this look correct to you? (to multiply 32.768 XT1 up to 8.00MHz?)

What is the actual multiplied frequency? (I make it 7929856 Hz)

Thanks in advance.

Regards,
Darren Start a New Thread