Reply by Nicholas O. Lindan●December 6, 20042004-12-06
"Deepu Talla" <a0216136@pixis.dal.design.ti.com> wrote
> The performance requirements of digital signal processing and embedded
> applications are rapidly increasing, but the power and cost budgets are
> decreasing. [What's an Engineer to do?]
First ask: Is this new product really necessary?
--
Nicholas O. Lindan, Cleveland, Ohio
Consulting Engineer: Electronics; Informatics; Photonics.
Remove spaces etc. to reply: n o lindan at net com dot com
psst.. want to buy an f-stop timer? nolindan.com/da/fstop/
Reply by Deepu Talla●December 6, 20042004-12-06
--
Call for papers:
================
*****************************************************************
3rd Workshop on Optimizations for DSP and Embedded Systems (ODES)
*****************************************************************
http://www.ece.vill.edu/~deepu/odes/odes.html
March 20, 2005
==============
Hotel Valencia Santana Row, San Jose, California
in conjunction with IEEE/ACM International Symposium on Code
Generation and Optimization (CGO)
http://www.cgo.org/
Submission deadline: January 14, 2005
=====================================
Call for papers
===============
The performance requirements of digital signal processing and embedded
applications are rapidly increasing, but the power and cost budgets are
decreasing. Optimization plays a very important role in managing the
conflicting demands. The focus of this workshop is to understand the
various optimization strategies applicable to the design of DSP and
embedded systems for performance,power, and cost.
Topics of Interest
==================
Topics of interest include, but are not limited to:
Algorithmic transformations and code/software optimization
Hardware and software optimizations for low-power consumption
and/or code density
Coprocessor and hardware accelerators
Compiler techniques and code generation for media processing
Frameworks for profiling and scheduling tasks (multiple/concurrent)
on various hardware resources (single-core + hardware
accelerators, dual-core, system-on-a-chip, etc)
Hardware/software tradeoffs with ASICs, FPGA's, DSPs,
general-purpose processors, microcontrollers, etc as building
blocks
Retargetable compilers and reconfigurable architectures
Important dates and deadlines
=============================
Submission: January 14, 2005
Acceptance: February 21, 2005
Final version: March 4, 2005
Submission guidelines
=====================
To encourage participation from both academia and industry, we are
requesting submissions in either of two formats:
A full paper, not exceeding 10 pages in length, two-column formatting
preferred. It is expected that an accepted submission of this type
will result in a final paper appearing in the workshop's proceedings
OR
A set of slides, along with a brief description (1-2 pages) of the
main theme of the talk. It is expected that an accepted submission of
this type will result in a talk abstract and a set of slides
appearing in the workshop's proceedings
Include the list of authors and their affiliations, addresses,
telephone and fax numbers, email addresses and the name of the
corresponding author. Please send the submission/s by the deadline to:
Deepu Talla via email at deepu@ti.com.
Program Co-chairs
=================
Deepu Talla deepu@ti.com Texas Instruments
Lizy John ljohn@ece.utexas.edu University of Texas at Austin
Program Committee
=================
Shuvra Bhattacharrya University of Maryland
Henk CorporaalTechnical University Eindhoven
Alex Dean NC State University
Pradeep Dubey Intel Corp
Jose Fridman Analog Devices
Jason Fritts Washington University in St. Louis
Tor Jeremiassen Texas Instruments
Eugene John University of Texas at San Antonio
Trevor Mudge University of Michigan
Vijay Narayanan Penn State University
John Reekie University of Technology Sydney
Scott Rixner Rice University
Past Workshops
==============
ODES-1: http://www.ece.vill.edu/~deepu/odes/odes-1_program.html
ODES-2: http://www.ece.vill.edu/~deepu/odes/odes-2_program.html