ashwin wrote:
> Hello Everyone,
>  I have few questions regarding the DP83847 PHY. I have this PHY on
> xilinx virtex fpga board.
>  I need to write an ethernet mac in the fpga to send the packets to the
> PC through the PHY. Initially, to start with i am implementing the
> transmit module.
>  1) when i hardware reset the PHY, the link estabilishes between the PC
> and the fpga board, but whatever data i put on the MII interface on the
> TXD(3:0), i am not able to see anything       when   i check the pin
> TD+- in the oscilloscope. For some reason the PHY is not transmitting
> the data.
>     a) Do i need to initialize the PHY before/after i hardware reset
> it. If yes how?
>     b) By default , if i  hardware reset, the PHY will act in 100 mbps
> full duplex mode.  So i guess , just to test this  PHY, i dont  have to
> use MDC and MDIO right?
>     c)Do i need to exactly send the ethernet  packet format to the PHY
> inorder to test it correctly with the oscilloscope or  will i be able
> to see any data if i check it in the oscilloscope?
>     d) will i see a sinusoid on the TD+ pin when i check it in the
> oscilloscope or is it a square wave.
> 
>  I would appreciate , if you could please answer my questions as soon
> as possible.
> 
> thanks
> ashwin
> 

Have you looked at the datasheet?
http://www.national.com/ds/DP/DP83847.pdf

I have never used the MII interface but I think that you need to do some 
kind of handshaking with the PHY chip before you can transmit data.

Rune Christensen
Engineer

"ashwin" <achiluka@gmail.com> wrote in message 
news:1130517373.081707.282880@g44g2000cwa.googlegroups.com...
> Hello Everyone,
> I have few questions regarding the DP83847 PHY. I have this PHY on
> xilinx virtex fpga board.
> I need to write an ethernet mac in the fpga to send the packets to the
> PC through the PHY. Initially, to start with i am implementing the
> transmit module.
> 1) when i hardware reset the PHY, the link estabilishes between the PC
> and the fpga board, but whatever data i put on the MII interface on the
> TXD(3:0), i am not able to see anything       when   i check the pin
> TD+- in the oscilloscope. For some reason the PHY is not transmitting
> the data.
>    a) Do i need to initialize the PHY before/after i hardware reset
> it. If yes how?

Possibly.  Any initialization you would do would be accomplished by 
setting/clearing bits in the MII registers.  You access these registers 
though the MDC and MDIO pins (the MIIM interface).

>    b) By default , if i  hardware reset, the PHY will act in 100 mbps
> full duplex mode.  So i guess , just to test this  PHY, i dont  have to
> use MDC and MDIO right?

That depends.  What do you have the PHYADDR0, ..., PHYADDR4 pins connected 
to?  They better not be all connected such that the address 0x0 is strapped 
into the PHYADDR bits of the PHYCTRL register.  Quickly scanning through the 
data sheet, I do not see any explicit need to write to any registers if your 
pins are connected properly, although I might have missed something.

>    c)Do i need to exactly send the ethernet  packet format to the PHY
> inorder to test it correctly with the oscilloscope or  will i be able
> to see any data if i check it in the oscilloscope?

The PHY has no idea what a proper Ethernet packet looks like, nor does it 
care.

>    d) will i see a sinusoid on the TD+ pin when i check it in the
> oscilloscope or is it a square wave.

Are you talking about the TD pins themselves, or the TX+/TX- pins on the 
cable side of the transmit transformer?  I'd recommend measuring the cable 
side of the transmit transformer.  This way, anything you do see will be 
directly comparable to other people's measurements, and you will get 
consistent results.  I believe the transformers are driven by current, not 
voltage, so measuring the TD pins themselves might varry, depending on what 
kind of transformer you have, what load is attached to the transformer, etc.

At 100Mbps, I don't think you'll see either a sinusoid or a square wave (on 
the cable side of the transformer).  I think you'll see trapezoids.  If I 
recall correctly, I think you'll see a slew rate limited rise/fall, followed 
by a steady voltage for a while, and then another slew rate limited 
fall/rise.

At 10Mbps, you would see sinusoid-like signals, depending on the bit pattern 
being transmitted.

Even if your FPGA isn't attached to the PHY (TX_CLK is running, but TX_EN is 
always deasserted), I think you should see these trapezoids comming out of 
the 100Mbps PHY.  This constant idle transmission is used to detect a link 
partner, and when connected, maintain RX clock synchronization.  Attach your 
oscilloscope to your PC's Ethernet card (by tapping into a cable or the pins 
on the RJ45 connector) to get an idea what these look like.  If your pins 
are silent, you probably have some hardware configuration or PHY 
initialization problem.  This would not imply an FPGA code problem. 

Hello Everyone,
 I have few questions regarding the DP83847 PHY. I have this PHY on
xilinx virtex fpga board.
 I need to write an ethernet mac in the fpga to send the packets to the
PC through the PHY. Initially, to start with i am implementing the
transmit module.
 1) when i hardware reset the PHY, the link estabilishes between the PC
and the fpga board, but whatever data i put on the MII interface on the
TXD(3:0), i am not able to see anything       when   i check the pin
TD+- in the oscilloscope. For some reason the PHY is not transmitting
the data.
    a) Do i need to initialize the PHY before/after i hardware reset
it. If yes how?
    b) By default , if i  hardware reset, the PHY will act in 100 mbps
full duplex mode.  So i guess , just to test this  PHY, i dont  have to
use MDC and MDIO right?
    c)Do i need to exactly send the ethernet  packet format to the PHY
inorder to test it correctly with the oscilloscope or  will i be able
to see any data if i check it in the oscilloscope?
    d) will i see a sinusoid on the TD+ pin when i check it in the
oscilloscope or is it a square wave.

 I would appreciate , if you could please answer my questions as soon
as possible.

thanks
ashwin