Reply by Robert Adsett February 3, 20092009-02-03
jtd wrote:
> I mean the internal pullup resistor in the micon. Afaik it is 50K ohm
> or so and wont drive a wire more than a few inches long.
> Put a 4K7 pullup resistor. I am presuming that the port is quasi.

I've not seen any QBD I/O on the LPC series (thank heavens).

BTW, all the QBDs I've seen use totem pole outputs with a current
foldback on the high side. None have used simple pull-up resistors.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."

An Engineer's Guide to the LPC2100 Series

Reply by Robert Adsett February 3, 20092009-02-03
jdauchot wrote:
> Thanks for all the help for this poblem.
>
> I would like to replace a 8032 cpu card, but retain the IO
> subsystems.
>
> What I have done so far is to removed the 8032 CPU,RAM , EPROM, RTC
> and ADC chips from the original CPU Card and soldered in a rubbon
> wired interface to the LPC2148 demo board and the 8032 pins. It
> interface to an existing front panel interface with an old LED
> display and keypad, IO interface etc.
>
> I have amulated the 8032 bus interface within the LC2148's using P0
> and P1 IO ports. written the drivers etc OK. The only problems that I
> have some spurious glithes accuring on one of the IO sub system.
>
> Aventually I will have to design a CPU card to interface with that
> lot.
>
> Sounds crazy

That depends on what you are attempting to achieve. As a learning
project it sounds as good as any. Also reasonable if you are aiming to
upgrade capabilities or maintainability or eliminate EOL parts.

If you're just replacing the 8032 there may be better uses of your time :)

BTW, watch the rest of the I/O, there is likely to be more that's
expecting 5V and is marginal or worse at lower voltages.

Robert

--
http://www.aeolusdevelopment.com/

From the Divided by a Common Language File (Edited to protect the guilty)
ME - "I'd like to get Price and delivery for connector Part # XXXXX"
Dist./Rep - "$X.XX Lead time 37 days"
ME - "Anything we can do about lead time? 37 days seems a bit high."
Dist./Rep - "that is the lead time given because our stock is live....
we currently have stock."

Reply by jdauchot February 3, 20092009-02-03
Thanks for all the help for this poblem.

I would like to replace a 8032 cpu card, but retain the IO
subsystems.

What I have done so far is to removed the 8032 CPU,RAM , EPROM, RTC
and ADC chips from the original CPU Card and soldered in a rubbon
wired interface to the LPC2148 demo board and the 8032 pins. It
interface to an existing front panel interface with an old LED
display and keypad, IO interface etc.

I have amulated the 8032 bus interface within the LC2148's using P0
and P1 IO ports. written the drivers etc OK. The only problems that I
have some spurious glithes accuring on one of the IO sub system.

Aventually I will have to design a CPU card to interface with that
lot.

Sounds crazy

Regards

--- In l..., "subscriptions@..."
wrote:
>
> jdauchot Wrote
> >I am not sure as I have no control over the receiving hardware and
no
> >info on the way it work.
>
> There's the first problem.
>
> >The only way I know it works its looking at a scope using the old
CPU
> >8032 based hardware. Its a train of 8x 9 bit data packets starting
> >with a start bit (positive)on each data packet. It ends with a
20ms
> >gap. Each pulse has to be 1ms. Each bit of the remaining data
packet
> >fires a relays on the receiving sub system(PIC Based). If the
system
> >stop sending the data packets, the IO sub system will go into a
fail
> >safe mode (drop all outputs). However. on the new hardware the IO
> >relays seem to fire randomly suggesting that the start bit is
> >expanding in some way due to drift of the PLL
>
> Given that description I would be surprised if drift was an issue.
I would
> expect it to re-sync on each 'start' pulse unless it was a really
brittle
> design. So drift should be important over a 72ms period. That's
short for
> a crystal but long for a PLL.
>
> My guess (and that's what it is) would be anything less than 1/3 of
a ms
> over 72 (or 0.5%) should work. That's a lot of drift.
>
> Given the relative age of the systems have you checked the input
voltage
> thresholds? It's a good chance the receiving system is expecting a
TTL
> drive at 5V. In which case you need a driver, something like a HCT
logic
> chip running off of 5V. Break open your test system and see what
the input
> circuits look like.
>
> You could play around with pulse sizes to get a fell of your
leeway. In
> fact that's a good idea anyway. That way at least you'll have some
> documentation.
>
> Robert
>
> Regards
>
> Jean-Jacques
>
>
>
> --- In l..., Robert Adsett
> wrote:
> >
> > jdauchot wrote:
> > > OK how do I grandee this 1ms pulse not drifting
> >
> > To what accuracy?
> >
> > Robert
> >
> > http://www.aeolusdevelopment.com/
> >
> > From the Divided by a Common Language File (Edited to protect
the
> guilty)
> > ME - "I'd like to get Price and delivery for connector Part #
XXXXX"
> > Dist./Rep - "$X.XX Lead time 37 days"
> > ME - "Anything we can do about lead time? 37 days seems a bit
> high."
> > Dist./Rep - "that is the lead time given because our stock is
> live....
> > we currently have stock."
> >
>
>
>
>
>
>
Reply by "sub...@aeolusdevelopment.com" February 3, 20092009-02-03
jdauchot Wrote
>The OP Subsystem has an optical isolator input on each card and has a
>small selector switch which determinites which octet of outputs to
>use. The siganl is daisy chained to the next card without
>amplification.
>
>It works fine using the old 80C32 processor card which has 5V output
>to drive that signal.

There's your problem. It's more surprising that it's working at all then
that you are seeing problems. You need a driver. Something like a
74HCT14's. Run one inverter after the other to keep the original polarity.
Use a 5V supply on the HCT14's and rely on the input thresholds of the
HCT14 to convert the LPC's 3V3 to 5V.

>Would using the fast IO on the LPC2148 improve
things?

Not even a little bit. Reducing the time it takes for a write operation
does not affect the drive capability of the pin.

Robert
--------------------------------
mail2web.com Enhanced email for the mobile individual based on Microsoft
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Reply by "sub...@aeolusdevelopment.com" February 3, 20092009-02-03
jdauchot Wrote
>I am using the IAR LPC2148 Kickstart demo board and I am driving the
>IO sub system by pulsing P1.25 via a timer0 1ms interrupt. The P1
>port is configured in GPIO. I will try using FGPIO, would that
>improve the rise time.

Why would that improve the rise time?

Robert
--------------------------------
mail2web.com What can On Demand Business Solutions do for you?
http://link.mail2web.com/Business/SharePoint

Reply by "sub...@aeolusdevelopment.com" February 3, 20092009-02-03
jdauchot Wrote
>I am using the IAR LPC2148 Kickstart demo board and I am driving the
>IO sub system by pulsing P1.25 via a timer0 1ms interrupt. The P1
>port is configured in GPIO. I will try using FGPIO, would that
>improve the rise time.

Why would that improve the rise time?

Robert
--------------------------------
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hosting - http://link.myhosting.com/myhosting

Reply by "sub...@aeolusdevelopment.com" February 3, 20092009-02-03
jtd Wrote
>Are the ports pushpull.

The only I/O ports on the LPC I'm aware of that aren't standard totem-pole
outputs are the IIC pins.

Robert

--------------------------------
mail2web.com What can On Demand Business Solutions do for you?
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Reply by "sub...@aeolusdevelopment.com" February 3, 20092009-02-03
jdauchot Wrote
>I am not sure as I have no control over the receiving hardware and no
>info on the way it work.

There's the first problem.

>The only way I know it works its looking at a scope using the old CPU
>8032 based hardware. Its a train of 8x 9 bit data packets starting
>with a start bit (positive)on each data packet. It ends with a 20ms
>gap. Each pulse has to be 1ms. Each bit of the remaining data packet
>fires a relays on the receiving sub system(PIC Based). If the system
>stop sending the data packets, the IO sub system will go into a fail
>safe mode (drop all outputs). However. on the new hardware the IO
>relays seem to fire randomly suggesting that the start bit is
>expanding in some way due to drift of the PLL

Given that description I would be surprised if drift was an issue. I would
expect it to re-sync on each 'start' pulse unless it was a really brittle
design. So drift should be important over a 72ms period. That's short for
a crystal but long for a PLL.

My guess (and that's what it is) would be anything less than 1/3 of a ms
over 72 (or 0.5%) should work. That's a lot of drift.

Given the relative age of the systems have you checked the input voltage
thresholds? It's a good chance the receiving system is expecting a TTL
drive at 5V. In which case you need a driver, something like a HCT logic
chip running off of 5V. Break open your test system and see what the input
circuits look like.

You could play around with pulse sizes to get a fell of your leeway. In
fact that's a good idea anyway. That way at least you'll have some
documentation.

Robert

Regards

Jean-Jacques

--- In l..., Robert Adsett
wrote:
>
> jdauchot wrote:
> > OK how do I grandee this 1ms pulse not drifting
>
> To what accuracy?
>
> Robert
>
> http://www.aeolusdevelopment.com/
>
> From the Divided by a Common Language File (Edited to protect the
guilty)
> ME - "I'd like to get Price and delivery for connector Part # XXXXX"
> Dist./Rep - "$X.XX Lead time 37 days"
> ME - "Anything we can do about lead time? 37 days seems a bit
high."
> Dist./Rep - "that is the lead time given because our stock is
live....
> we currently have stock."
>

Reply by jtd February 3, 20092009-02-03
On Tuesday 03 February 2009 20:01, jdauchot wrote:
> The OP Subsystem has an optical isolator input on each card and has
> a small selector switch which determinites which octet of outputs
> to use. The siganl is daisy chained to the next card without
> amplification.

It wont work. You have to come up with a buffer / line driver scheme.

>
> It works fine using the old 80C32 processor card which has 5V
> output to drive that signal.

Those devices had fat output transistors and withstood much abuse. The
new devices have miniscule geometries and consequently (mostly) poor
driving capability for such applications.

> Would using the fast IO on the LPC2148
> improve things?

If it has a pushpull output.
--
Rgds
JTD

Reply by jdauchot February 3, 20092009-02-03
The OP Subsystem has an optical isolator input on each card and has a
small selector switch which determinites which octet of outputs to
use. The siganl is daisy chained to the next card without
amplification.

It works fine using the old 80C32 processor card which has 5V output
to drive that signal. Would using the fast IO on the LPC2148 improve
things?

Regards

--- In l..., jtd wrote:
>
> On Tuesday 03 February 2009 19:21, jdauchot wrote:
> > The P1.25 output signal goes to an input of a LM358 OP Amp via a
> > wire from a rubbon cable. It amplify the signal to 12V pulses.
>
> you will then shift it down to 5v for the input on the other side.
In
> which case you will have a skew in the clock relative to data,
> presuming that data is not following a similiar chain.
>
> >
> > There are no pull up resistor on that input.
>
> I mean the internal pullup resistor in the micon. Afaik it is 50K
ohm
> or so and wont drive a wire more than a few inches long.
> Put a 4K7 pullup resistor. I am presuming that the port is quasi.
In
> any case it wont harm, as the current draw on a low will be less
> around 700ua.
>
> > --- In l..., jtd wrote:
> > > On Tuesday 03 February 2009 13:52, jtd wrote:
> > > > On Tuesday 03 February 2009 12:25, jdauchot wrote:
> > > > > Thanks for all the responses
> > > > >
> > > > > I am using the IAR LPC2148 Kickstart demo board and I am
> > > > > driving the IO sub system by pulsing P1.25 via a timer0 1ms
> > > > > interrupt. The P1 port is configured in GPIO. I will try
> > > > > using FGPIO, would that improve the rise time. I am not a
> > > > > hardware engineer
> > > >
> > > > Are the ports pushpull. Afaik they are not and have a weak
> > > > pullup. Which means that the high to low transition will be
> > > > fast, but the low to high transition will be slow. If they are
> > > > not pushpull
> >
> > (also
> >
> > > > called quasi bidirectional) then adding a pull up of 4K7
should
> > > > improve things. Also if you are connecting to the other board
> >
> > using
> >
> > > > wires more than a few inches long you will have lots of
> > > > trouble. You will then need a driver (ls 244 /45 are a quick
> > > > dirty hack
> >
> > that
> >
> > > > always works).
> > >
> > > Big fat warning i have never used LPC2148.
> > >
> > > --
> > > Rgds
> > > JTD
>
> --
> Rgds
> JTD
>