--- In l..., "Chip Dyer" wrote: >
> I'm no expert... but I'll give this a shot. I have been
struggling
> with the same thing for a week...
>
> The dummy read is to set the MODE register of the SDRAM device. Since
> the LPC2478 MUX's the row and column address on the data bus, we need
> to shift that value to the proper bits
>
> Example: 4Mx32 part (MT48LC4M32B2) on a 32-bit bus.
> dwtemp = *((volatile INT32U *)(SDRAM_BASE | 0x00008800));
>
> Micron's data sheet for MT48LC4M32B2 indicates that the Mode register
> needs to be set to 0x022 for BURST=4, CAS=2, Sequential Burst,
> Standard operation at programmed burst length.
>
OK, looking at the same data sheet I see this setting is correct
> Setting the LPC2478 EMCDynamicConfig register for a
32-bit bus for a
> 128MB (4Mx32) part (BANK, ROW, COLUMN), the address line usage is as
So this would be AM bit pattern 1101001 (pg 88 in UM) good so far.
> follows:
> Row: A12:A0 >> [21:10]
> BA1:BA0 are mapped higher but need to be 0x00 anyway.
>
> So, the value 0x022 needs to be shifted to address bits 21:10, so
> shift the value left by 10 bits.
>
You have lost me. Why does it need to shift 10 bits? If the implied
order of the bits is BANK,ROW,COL, and your column field is 8bits, and
the mode reg value must be aligned with the 'row' bits to take,
then
your shift is 8bits.
Now BANK,ROW,COL or ROW,BANK,COL distinction is also confusing since
the address is not presented in one go. First the row and bank bits
are presented (I assume aligned to bit0), then the col bits are
presented (also I assume aligned to bit0).
I have to assume this is the internal address bit order before the EMC
does its multiplexing, but is it an order mandated by the sdram
design, or is it mandated by the EMC? I thought for instance, that on
some sdram you could do ras before cas or cas before ras, so that
would allow the EMC to do either presentation order and maybe the
internal address bit order would be different when you do.
Reply by Chutiman Yongprapat●February 13, 20092009-02-13
Excellent!!
You mean that, in case of BANK-ROW-COLUMN and 32 bit it must be COLUMN width
+ 2 (from 32 bit) right?
And for ROW-BANK-COLUMN 32 bit, it must be COLUMN width + BANK width (2 for
4 banks) + 2 (from 32 bit).
So in my case, I use 32 bit with 16Mx16 and ROW BANK COLUMN arrangement.
It must be COLUMN width + BANK width (2 for 4 banks) + 2 (from 32 bit)
=9+2+2
Many thanks
Chutiman
Reply by Chip Dyer●February 13, 20092009-02-13
I'm no expert... but I'll give this a shot. I have been struggling
with the same thing for a week...
The dummy read is to set the MODE register of the SDRAM device. Since
the LPC2478 MUX's the row and column address on the data bus, we need
to shift that value to the proper bits
Example: 4Mx32 part (MT48LC4M32B2) on a 32-bit bus.
dwtemp = *((volatile INT32U *)(SDRAM_BASE | 0x00008800));
Micron's data sheet for MT48LC4M32B2 indicates that the Mode register
needs to be set to 0x022 for BURST=4, CAS=2, Sequential Burst,
Standard operation at programmed burst length.
Setting the LPC2478 EMCDynamicConfig register for a 32-bit bus for a
128MB (4Mx32) part (BANK, ROW, COLUMN), the address line usage is as
follows:
Row: A12:A0 >> [21:10]
BA1:BA0 are mapped higher but need to be 0x00 anyway.
So, the value 0x022 needs to be shifted to address bits 21:10, so
shift the value left by 10 bits.
Setting the LPC2478 EMCDynamicConfig register for the same part but
for (ROW,BANK,COLUMN), the address line usage is as follows:
Row: A12:A0 >> [23:12]
So you would shift the value by 12 bits for this mode.
Chip
--- "tclarke1" wrote: >Chutiman Yongprapat wrote:
> > Do you mean something like :
> > dummy = *((volatile unsigned long *)(SDRAM_BASE_ADDR | (0x11 << 12)));
> > As I told above that we have to set some registers in SDRAM. In >
> MT48LC16M16A2, page 18 of datasheet describes about this setting
> OK, I can see that bus bits A14:A0 correspond to
BA1:BA0:A12:A0, and
> that if the bus is in that special state which allows it
> (CS#,RAS#,CAS#,WE# are all asserted - I assume that asserting WE# on a
> read cycle has something to do with those EMC_DYN_CTRL reg settings),
> the lower 10bits are then used to set the sdram mode register. But
> this does not explain why the code x11 << 12 also seems concerned with
> bits A16:A15 which are not even connected to the sdram. How is that
> explained?
Reply by tclarke1●February 13, 20092009-02-13
--- In l..., Chutiman Yongprapat wrote: >
> Do you mean something like :
>
> dummy = *((volatile unsigned long *)(SDRAM_BASE_ADDR | (0x11 << 12)));
>
> As I told above that we have to set some registers in SDRAM. In case of
> MT48LC16M16A2, page 18 of datasheet describes about this setting which
> include write burst mode, operation mode, CAS latency, burst type and burst > length.
> You may notice that we have to set DYN_CTRL before reading, something like : >
> EMC_DYN_CTRL = 0x00000083;
>
> This will cause the operation mode to command mode (bit 7-8).
>
> Best Regards,
> Chutiman
>
> OK, I can see that bus bits A14:A0 correspond to BA1:BA0:A12:A0, and
that if the bus is in that special state which allows it
(CS#,RAS#,CAS#,WE# are all asserted - I assume that asserting WE# on a
read cycle has something to do with those EMC_DYN_CTRL reg settings),
the lower 10bits are then used to set the sdram mode register. But
this does not explain why the code x11 << 12 also seems concerned with
bits A16:A15 which are not even connected to the sdram. How is that
explained?
Reply by Chutiman Yongprapat●February 13, 20092009-02-13
Do you mean something like :
dummy = *((volatile unsigned long *)(SDRAM_BASE_ADDR | (0x11 << 12)));
As I told above that we have to set some registers in SDRAM. In case of
MT48LC16M16A2, page 18 of datasheet describes about this setting which
include write burst mode, operation mode, CAS latency, burst type and burst
length.
You may notice that we have to set DYN_CTRL before reading, something like :
EMC_DYN_CTRL = 0x00000083;
This will cause the operation mode to command mode (bit 7-8).
Best Regards,
Chutiman
Reply by tclarke1●February 12, 20092009-02-12
--- In l..., Chutiman Yongprapat wrote: >
> Hi,
> It depends on row address width of your SDRAM. In my case, MT48LC16M16A2 has > A0-A12 then I have to shift 13 times. Before I try
13, I have problem that a > double-word write (I use 32 bit wide) cause 4
double-word in adjacent
> address effect (imagine that you write address 0 only, but address 0-3
> effected).
>
> This is something about writing command to SDRAM, the command parameter is > accepted via address bus. To do that, you have to
shift them out off your > internal address which is set when you write to
EMC_DYN_CFG0.
>
> Thanks to this web board that I found someone talked about this topic,
> unless it's hard to find description about the topic.
> Best Regards,
> Chutiman Yongprapat
> Venus Supply co., ltd.
> 196/1, Soi Thedsaban-Nimit-Nau 8,
> Thedsaban-Nimit-Nau Road, Ladyao,
> Chatuchak, Bangkok 10900 Thailand
> www.ThaiEasyElec.com
> Tel. 086-5036512
> E-mail: chutiman@...
>
>
I was about to ask the same question about that strange line of code
in the sdram initialization. It looks like a 32bit read at sdram
offset 0x11000 which seems to have no purpose. If this is really
setting a register in the sdram or processor, I'd like to hear an
explanation of how it works. Is there an alternate method to do the same?
Reply by Chutiman Yongprapat●February 12, 20092009-02-12
Hi,
It depends on row address width of your SDRAM. In my case, MT48LC16M16A2 has
A0-A12 then I have to shift 13 times. Before I try 13, I have problem that a
double-word write (I use 32 bit wide) cause 4 double-word in adjacent
address effect (imagine that you write address 0 only, but address 0-3
effected).
This is something about writing command to SDRAM, the command parameter is
accepted via address bus. To do that, you have to shift them out off your
internal address which is set when you write to EMC_DYN_CFG0.
Thanks to this web board that I found someone talked about this topic,
unless it's hard to find description about the topic.
Best Regards,
Chutiman Yongprapat
Venus Supply co., ltd.
196/1, Soi Thedsaban-Nimit-Nau 8,
Thedsaban-Nimit-Nau Road, Ladyao,
Chatuchak, Bangkok 10900 Thailand
www.ThaiEasyElec.com
Tel. 086-5036512
E-mail: c...@thaieasyelec.com
Reply by sachin dhiman●February 12, 20092009-02-12
do u want to know what will be the result of 0x22<<11;
if yes, then here is solution...
0x22<<11
or
0x00000022 <<11
and answer is
0x00011000
I hope this will help
On Wed, Feb 11, 2009 at 1:42 PM, seansonpizza wrote:
> Hi to all,
> i'm using LPC2478 and i have some questions about sdram
initialization:
> 1)shift value...for example:
> dummy = *((volatile unsigned int*)(SDRAM_BASE_ADDR | (0x22 << 11)));
> why 11? I have found a lot of topics that explain how calculate it,
> but where can find technical reference that explains it? PL172
> technical reference nothing said about it....I'm looking for a
> technical reference that explain why shift value is used and how
> calculate it (in this group i have found some answers, but i'm looking
> for sources used for these answers)
> 2)i don't understand how arm technical references are called: for
> example, i've found 4 technical references (PL170,PL172,PL175,PL176)
> for memory controller...What is the right reference for lpc2478?Why?
> thanks
>
>
>
--
Kind Regards
Sachin Dhiman
Reply by seansonpizza●February 11, 20092009-02-11
Hi to all,
i'm using LPC2478 and i have some questions about sdram initialization:
1)shift value...for example:
dummy = *((volatile unsigned int*)(SDRAM_BASE_ADDR | (0x22 << 11)));
why 11? I have found a lot of topics that explain how calculate it,
but where can find technical reference that explains it? PL172
technical reference nothing said about it....I'm looking for a
technical reference that explain why shift value is used and how
calculate it (in this group i have found some answers, but i'm looking
for sources used for these answers)
2)i don't understand how arm technical references are called: for
example, i've found 4 technical references (PL170,PL172,PL175,PL176)
for memory controller...What is the right reference for lpc2478?Why?
thanks
