> Hi Everyone
>
> In the case of a simple configuration comprising a CMOS microprocessor
> plus one external CMOS SRAM, it may well happen that the processor's
> external bus interface becomes inactive for long periods (for instance,
> when the uP is accessing code and data in internal memory).
>
> In this case, the bus is high impedance, and could, in principle, float
> to a voltage mid-way between the power rails. This would cause both p-
> and n-channel devices of any CMOS input buffer connected to the bus to
> partially conduct, resulting in increased dissipation and possible
> device damage. Are devices designed to be connected to data buses
> somehow protected against this problem, or should the bus be pulled up
> or down with resistors?
>
> TIA
> Geoff
For data busses, this is not an issue (the RAM DQ pins are tristated
unless accessed, specifically because they are expected to be on
floating circuits), but would be an issue for control and address,
which are standard inputs on the RAM. I have had this problem on a
*very* old microcontroller (CMD 65151 / 65150) which would tristate the
address bus outputs when not accessing externally.
The only time a modern controller / processor should tristate the
address and control bus is if it is capable of granting the bus to
another bus master and actually does so, but I don't know what
processor you are using, which would be a help.
To get around this at low speeds (up to perhaps 4MHz) use pullups or
pulldowns (doesn't really matter which, usually except for the control
pins which should be pulled to their inactive state) or use bus drivers
with bus hold circuitry (as someone already mentioned but is more
expensive and more complicated).
Cheers
PeteS
Reply by ●February 21, 20062006-02-21
Geoffrey wrote:
> Hi Everyone
>
> In the case of a simple configuration comprising a CMOS microprocessor
> plus one external CMOS SRAM, it may well happen that the processor's
> external bus interface becomes inactive for long periods (for instance,
> when the uP is accessing code and data in internal memory).
>
> In this case, the bus is high impedance, and could, in principle, float
> to a voltage mid-way between the power rails. This would cause both p-
> and n-channel devices of any CMOS input buffer connected to the bus to
> partially conduct, resulting in increased dissipation and possible
> device damage. Are devices designed to be connected to data buses
> somehow protected against this problem, or should the bus be pulled up
> or down with resistors?
>
> TIA
> Geoff
A typical micro does not tristate the busses unless it gets a buss
request from another bus driver, ie a dma device, so the problem does
not arise.
Reply by Neil●February 21, 20062006-02-21
Geoffrey wrote:
> Hi Everyone
>
> In the case of a simple configuration comprising a CMOS microprocessor
> plus one external CMOS SRAM, it may well happen that the processor's
> external bus interface becomes inactive for long periods (for instance,
> when the uP is accessing code and data in internal memory).
>
> In this case, the bus is high impedance, and could, in principle, float
> to a voltage mid-way between the power rails. This would cause both p-
> and n-channel devices of any CMOS input buffer connected to the bus to
> partially conduct, resulting in increased dissipation and possible
> device damage. Are devices designed to be connected to data buses
> somehow protected against this problem, or should the bus be pulled up
> or down with resistors?
>
> TIA
> Geoff
>
Look at the data sheets. Chips designed for a bus should work on one.
Pull ups may slow down the bus.
What CPU or is this a general question?
Reply by Allan Herriman●February 20, 20062006-02-20
On 20 Feb 2006 09:08:52 -0800, "Geoffrey" <gmortimer@ferrari.it>
wrote:
>Hi Everyone
>
>In the case of a simple configuration comprising a CMOS microprocessor
>plus one external CMOS SRAM, it may well happen that the processor's
>external bus interface becomes inactive for long periods (for instance,
>when the uP is accessing code and data in internal memory).
>
>In this case, the bus is high impedance, and could, in principle, float
>to a voltage mid-way between the power rails. This would cause both p-
>and n-channel devices of any CMOS input buffer connected to the bus to
>partially conduct, resulting in increased dissipation and possible
>device damage. Are devices designed to be connected to data buses
>somehow protected against this problem, or should the bus be pulled up
>or down with resistors?
Another option is to use "keepers" or "bus holds" instead of pullups
or pulldowns.
One problem with pull up or down resistors is that the resistor must
be weak with respect to the driving logic. This leads to slow rise or
fall times when the driver is Hi-Z, and the signal stays in the
transition region for a relatively long time.
A keeper is just a non-inverting CMOS buffer with a very weak output
that is tied to its input. If the input is high, it pulls up. If the
input is low, it pulls down. The net result is that the signal stays
at the voltage (high or low) that it had when the strong driver went
Hi-Z.
Of course, you don't buy a "keeper" as a standalone component, but
some logic families (e.g. LVT) offer them as options on bus buffers,
etc. Since you possibly already have a buffer chip on this data bus,
it might be possible to add keepers by just changing a part number.
Regards,
Allan
Reply by Geoffrey●February 20, 20062006-02-20
That's what I'm assuming.
Reply by Tim Wescott●February 20, 20062006-02-20
Geoffrey wrote:
> Hi Everyone
>
> In the case of a simple configuration comprising a CMOS microprocessor
> plus one external CMOS SRAM, it may well happen that the processor's
> external bus interface becomes inactive for long periods (for instance,
> when the uP is accessing code and data in internal memory).
>
> In this case, the bus is high impedance, and could, in principle, float
> to a voltage mid-way between the power rails. This would cause both p-
> and n-channel devices of any CMOS input buffer connected to the bus to
> partially conduct, resulting in increased dissipation and possible
> device damage. Are devices designed to be connected to data buses
> somehow protected against this problem, or should the bus be pulled up
> or down with resistors?
>
> TIA
> Geoff
>
I was taught that such buses should always have pull ups (or pull downs)
on them. Dunno if they're still necessary -- but I bet they are.
My first for-money processor board used a 68HC11F part, with expansion
bus. Some of the control lines were open-drain, which I didn't catch
until _after_ the board was done and I'd spent 2 weeks of debugging.
Gee did I feel stupid. Gee, haven't I been diligent ever since about
pull ups.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Posting from Google? See http://cfaj.freeshell.org/google/
Reply by larwe●February 20, 20062006-02-20
Geoffrey wrote:
> plus one external CMOS SRAM, it may well happen that the processor's
> external bus interface becomes inactive for long periods (for instance,
> when the uP is accessing code and data in internal memory).
During this condition, the select and write/read strobes on the
appropriate memory device are also not asserted, right?
Reply by Geoffrey●February 20, 20062006-02-20
Hi Everyone
In the case of a simple configuration comprising a CMOS microprocessor
plus one external CMOS SRAM, it may well happen that the processor's
external bus interface becomes inactive for long periods (for instance,
when the uP is accessing code and data in internal memory).
In this case, the bus is high impedance, and could, in principle, float
to a voltage mid-way between the power rails. This would cause both p-
and n-channel devices of any CMOS input buffer connected to the bus to
partially conduct, resulting in increased dissipation and possible
device damage. Are devices designed to be connected to data buses
somehow protected against this problem, or should the bus be pulled up
or down with resistors?
TIA
Geoff