i found the question?
/*********************************************************************
*
* execUserReset() : JTAG set initially to Full Speed
*/
execUserReset() {
__message "execUserReset()";
_InitPLL(); // Allow to debug at JTAG Full Speed
_MapRAMAt0(); // Remap SRAM to address 0
}
_MapRAMAt0(); // Remap SRAM to address 0
this should commented...
--- In A..., "jechern@..." wrote:
>
> now , i can run uc os in the sdram ,but it have a new problem,
> it always ends in adress 0x071e , and i don't know why?(55.... -D)
>
> this is my iar .icf file:
> /*###ICF### Section handled by ICF editor, don't touch! ****/
> /*-Editor annotation file-*/
> /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
> /*-Memory Regions-*/
> define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
> define symbol __ICFEDIT_region_ROM_end__ = 0x20FFFFFF;
> define symbol __ICFEDIT_region_SDRAM_start__ = 0x21000000;
> define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF;
> define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
> define symbol __ICFEDIT_region_RAM_end__ = 0x201FFF;
> /*-Sizes-*/
> define symbol __ICFEDIT_size_startup__ = 0x100;
> define symbol __ICFEDIT_size_vectors__ = 0x100;
> define symbol __ICFEDIT_size_cstack__ = 0x400;
> define symbol __ICFEDIT_size_svcstack__ = 0x100;
> define symbol __ICFEDIT_size_irqstack__ = 0x400;
> define symbol __ICFEDIT_size_fiqstack__ = 0x100;
> define symbol __ICFEDIT_size_undstack__ = 0x40;
> define symbol __ICFEDIT_size_abtstack__ = 0x40;
> define symbol __ICFEDIT_size_heap__ = 0x400;
> /*-Exports-*/
> /*
> export symbol __ICFEDIT_region_SDRAM_start__;
> export symbol __ICFEDIT_region_SDRAM_end__;
> export symbol __ICFEDIT_region_RAM_start__;
> export symbol __ICFEDIT_region_RAM_end__;
> export symbol __ICFEDIT_size_startup__;
> export symbol __ICFEDIT_size_vectors__;
> export symbol __ICFEDIT_size_cstack__;
> export symbol __ICFEDIT_size_sysstack__;
> export symbol __ICFEDIT_size_irqstack__;
> export symbol __ICFEDIT_size_heap__;
> */
> /**** End of ICF editor section. ###ICF###*/
>
> define memory mem with size = 4G;
> define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size
__ICFEDIT_size_startup__];
> define region ROM_region = mem:[from
__ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to
__ICFEDIT_region_ROM_end__];
> define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__ to
__ICFEDIT_region_SDRAM_end__];
> define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size
__ICFEDIT_size_vectors__];
> define region RAM_region = mem:[from
__ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to
__ICFEDIT_region_RAM_end__];
>
> define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {
};
> define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ {
};
> define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {
};
> define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ {
};
> define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ {
};
> define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ {
};
> define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ {
};
>
> initialize by copy { section .intvec };
> do not initialize { section .noinit };
>
> place in STA_region { section text };
> place in VEC_region { section .intvec };
> place in ROM_region { readonly };
> place in SDRAM_region { readwrite, block CSTACK, block SVC_STACK, block
IRQ_STACK, block FIQ_STACK,
> block UND_STACK, block ABT_STACK, block HEAP };
>
> and the iar .mac file:
> // ----------------------------------------
> // ATMEL Microcontroller Software Support - ROUSSET -
> // ----------------------------------------
> // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS
OR
> // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF
> // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
ARE
> // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
> // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT
> // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA,
> // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
OF
> // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE,
> // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> // ----------------------------------------
> // File Name : SAM7SE_SDRAM.mac
> // Object : Generic Macro File for IAR
> // 1.0 17/Aug/05 FBr : Creation
> // ----------------------------------------
>
> __var __mac_i;
> __var __mac_mem;
> __var __mac_next;
>
> /*********************************************************************
> *
> * _MapFlashAt0()
> *
> * Function description
> * Maps FLASH at 0.
> */
> _MapFlashAt0(){
> __mac_mem =__readMemory32(0x00000000,"Memory");
> __mac_i =__mac_mem+1;
> __writeMemory32(__mac_i,0x00,"Memory");
> __mac_next =__readMemory32(0x00000000,"Memory");
>
> if (__mac_i == __mac_next) {
> __writeMemory32( __mac_mem,0x00000000,"Memory");
> __message "Changing mapping: mapping FLASH at 0x0000_0000";
> __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
> __message "RAM at 0x0000_0000";
> } else {
> __message "Flash is mapped at 0x0000 0000";
> }
> }
>
> /*********************************************************************
> *
> * _MapRAMAt0()
> *
> * Function description
> * Maps RAM at 0.
> */
> _MapRAMAt0(){
> __message "Changing mapping: RAM mapped to 0";
> __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
> }
>
> /*********************************************************************
> *
> * __initSDRAM()
> * Function description
> * Set SDRAM for works at 48 MHz
> */
> __initSDRAM()
> {
> //* Enable clock on EBI pios
> // pPMC->PMC_PCER = AT91C_EBI_CS1A_SDRAMC;
> // PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC_PCER) Peripheral Clock
Enable Register
> __writeMemory32(0x0000001C,0xFFFFFC10,"Memory");
>
> //* Configure PIOs
> __writeMemory32(0x00000000,0xFFFFF470,"Memory");
> __writeMemory32(0x3F800000,0xFFFFF474,"Memory");
> __writeMemory32(0x3F800000,0xFFFFF404,"Memory");
>
> __writeMemory32(0x00000000,0xFFFFF670,"Memory");
> __writeMemory32(0x0003FFFF,0xFFFFF674,"Memory");
> __writeMemory32(0x0003FFFF,0xFFFFF604,"Memory");
>
> __writeMemory32(0x0000FFFF,0xFFFFF870,"Memory");
> __writeMemory32(0x00000000,0xFFFFF874,"Memory");
> __writeMemory32(0x0000FFFF,0xFFFFF804,"Memory");
>
> //* Configure EBI Chip select
> // pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
> // AT91C_CCFG_EBICSA ((AT91_REG *) 0xFFFFEF1C) // (CCFG) EBI Chip Select
Assignement Register
> __writeMemory32(0x02,0xFFFFFF80,"Memory");
>
> //* psdrc->SDRC_CR = AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 |
AT91C_SDRAMC_CAS_2 |
> // AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_4 |
> // AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_3 |
AT91C_SDRAMC_TXSR_4 ;
> __writeMemory32(0x21922159,0xFFFFFFB8,"Memory");
>
> __sleep(200);
>
> //* psdrc->SDRC_MR = 0x00000011; // NOP CMD
> __writeMemory32(0x00000011,0xFFFFFFB0,"Memory");
> //* *AT91C_SDRAM = 0x00000000;
> __writeMemory32(0x00000000,0x20000000,"Memory");
>
> //* psdrc->SDRC_MR = 0x00000012; // Perform PRCHG
> __writeMemory32(0x00000012,0xFFFFFFB0,"Memory");
> //* *AT91C_SDRAM = 0x00000000;
> __writeMemory32(0x00000000,0x20000000,"Memory");
>
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
> __writeMemory32(0x0000014,0xFFFFFFB0,"Memory");
> __writeMemory32(0x00000000,0x20000000,"Memory");
>
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
> __writeMemory32(0x00000013,0xFFFFFFB0,"Memory");
> //* *(AT91C_SDRAM+0x20) = 0xcafedede; // Perform LMR burst=1, lat=2
> __writeMemory32(0xCAFEDEDE,0x20000020,"Memory");
>
> //* psdrc->SDRC_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
> __writeMemory32(0x00000010,0xFFFFFFB0,"Memory");
>
> //* psdrc->SDRC_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer
390 for 25MHz (TR= 15.6 * F )
> // // (F : system clock freq. MHz
> __writeMemory32(0x00000150,0xFFFFFFB4,"Memory");
>
> //* *AT91C_SDRAM = 0x00000000; // Perform Normal mode
> __writeMemory32(0x00000000,0x20000000,"Memory");
>
> __message "------------------------------- SDRAM Done at 48 MHz
-------------------------------";
> }
>
>
> /*********************************************************************
> *
> * _InitRSTC()
> *
> * Function description
> * Initializes the RSTC (Reset controller).
> * This makes sense since the default is to not allow user resets, which
makes it impossible to
> * apply a second RESET via J-Link
> */
> _InitRSTC() {
> __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory"); // Allow user
reset
> }
>
> /*********************************************************************
> *
> * _InitPLL()
> * Function description
> * Initializes the PMC.
> * 1. Enable the Main Oscillator
> * 2. Configure PLL to 96MHz
> * 3. Switch Master Clock (MCK) on PLL/2 = 48MHz
> */
> _InitPLL() {
> __message "Set Main Oscillator";
> __writeMemory32(0x00004001,0xFFFFFC20,"Memory"); // MOSC
> while( !(__readMemory32(0xFFFFFC68,"Memory") & 0x1) );
>
> __message "Set PLL to 96MHz";
> __writeMemory32(0x1048100e,0xFFFFFC2C,"Memory"); // LOCK
> while( !(__readMemory32(0xFFFFFC68,"Memory") & 0x4) );
>
> __message "Set Master Clock to 48MHz";
> __writeMemory32(0x00000004,0xFFFFFC30,"Memory"); // MCKRDY
> while( !(__readMemory32(0xFFFFFC68,"Memory") & 0x8) );
> __writeMemory32(0x00000007,0xFFFFFC30,"Memory"); // MCKRDY
> while( !(__readMemory32(0xFFFFFC68,"Memory") & 0x8) );
> }
>
> /*********************************************************************
> *
> * execUserReset() : JTAG set initially to Full Speed
> */
> execUserReset() {
> __message "execUserReset()";
> _InitPLL(); // Allow to debug at JTAG Full
Speed
> _MapRAMAt0(); // Remap SRAM to address 0
> }
>
> /*********************************************************************
> *
> * execUserPreload() : JTAG set initially to 32kHz
> */
> execUserPreload() {
> __message "execUserPreload()";
> __hwReset(0); // Hardware Reset: CPU is
automatically halted after the reset (JTAG is already configured to 32kHz)
> _InitPLL(); // Allow to load Code at JTAG Full
Speed
> __initSDRAM(); // Init SDRAM before load
> _MapRAMAt0(); // Remap SRAM to address 0
> _InitRSTC(); // Enable User Reset to allow
execUserReset() execution
> }
>
>
> --- In A..., "jechern@" wrote:
> >
> > Hi,everybody
> > my final result is communication over Ethernet using
> > TCP/IP. The TCP/IP stack I don't like to write by my own, therefore
> > I like to use usos with the tcp/ip. Has anybody experience with
> > this??
> > and i don't know how to port uc os into the at91sam7se32-ek board?
> > i found some useful information in this web site
> > http://www.micrium.com/atmel/AT91SAM7.html
> > but my board's core is at91sam7se32 not the at91sam7se512 , without
> > enough internel flash and internel sram to load the program.
> > can any body help me to change the iar xcl file to suit my board . let uc os
run in the sdram
> > (my board 's sdram is 32M bytes.)
> >
> > Thx
> >
> > have a fun day!~
> >
> > ----------------------------
> > Je.Chern
>