Hi,
Have some problem about SSP protocol with TDA1543
The problem appears as the last bits (low order)
are unordered, giving a distortion for low signals.
I had trying lot of configuration combinations
without results. Follow the source.
Appreciate any help. Tanks in advance.
Miguel
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// spi1.c - ARM7 lpc2148 - DAC with TDA1543
// P0.17 pin 47 SCK1
// P0.19 pin 54 MOSI1
// P0.20 pin 55 WS (L/R sel)
// Copyright (C) 2007 miguel angel labolida
// This program is under the terms of the GNU General Public License
// version 03 - 20090907
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#define _spi1_
#include "lpc214x.h"
#include "types.h"
#include "spi1.h"
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void spi1_ini(void)
{
// pin configuration
// P0.17 pin 47 SCK1 - PINSEL1 3:2 10 SCK1 (SSP)
PINSEL1 |= BIT3;
PINSEL1 &= ~BIT2;
// P0.19 pin 54 MOSI1 - PINSEL1 7:6 10 MOSI1 (SSP)
PINSEL1 |= BIT7;
PINSEL1 &= ~BIT6;
// P0.20 pin 55 WS(L/R) - PINSEL1 9:8 00 GPIO Port 0.20
PINSEL1 &= ~BIT9;
PINSEL1 &= ~BIT8;
IO0DIR |= BIT20; // output WS (L/R sel)
// register configuration
// SSPCR0 Control Register 0. clock rate, bus type, and data size.R/W
SSPCR0 =
// BIT2 | BIT1 | BIT0 // DSS 3:0 Data Size 0111=8bits
// BIT3 // DSS 3:0 Data Size 1000=9bits
// BIT3 | BIT0 // DSS 3:0 Data Size 1001=10bits
// BIT3 | BIT1 // DSS 3:0 Data Size 1010=11bits
BIT3 | BIT1 | BIT0 // DSS 3:0 Data Size 1011=12bits
// BIT3 | BIT2 // DSS 3:0 Data Size 1100=13bits
// BIT3 | BIT2 | BIT0 // DSS 3:0 Data Size 1101=14bits
// BIT3 | BIT2 | BIT1 // DSS 3:0 Data Size 1110=15bits
// BIT3 | BIT2 | BIT1 | BIT0 // DSS 3:0 Data Size 1111=16bits
// FRF 5:4 Frame Format.00=SPI
// | BIT4 // FRF 5:4 01=SSI Texas
// | BIT5 // FRF 5:4 10=Microwire
// FRF 5:4 11=not suported
// | BIT6 // CPOL 6 0:1st ck 1:2nd ck (SPI)
// | BIT7 // CPHA 7 0:low 1:high (SPI)
// SCR 15:8 Clock
// | 0x00000300; // SCR f= PCLK / (CPSDVSR *
[SCR+1])
| BIT8 // SCR 15:8 0x01
// | BIT9 // SCR 15:8 0x02
;
// SSPCR1 Control Register 1. Selects master/slave and other modes.R/W
SSPCR1 =
// BIT0 // LBM loopback 0:normal 1:invert
BIT1 // SSE 0:SSP disable 1:SSP enable
// | BIT2 // MS 0:master 1:slave (only SSE=0)
;
// SSPDR Data Register. Write FIFO, and reads FIFO.R/W
// SSPSR Status Register RO
// SSPCPSR Clock Prescale Register R/W
SSPCPSR =
0x0002 // CPSDVSR 7:0
;
// SSPIMSC Interrupt Mask Set and Clear Register R/W
SSPIMSC = 0;
// SSPRIS Raw Interrupt Status Register RO
// SSPMIS Masked Interrupt Status Register RO
// SSPICR SSPICR Interrupt Clear Register WO
/*
// TDA1543 max.ck 9.2 MHz
// TDA1311 max.ck 18.4 MHz
PCLK Pheripheral clock = 30 MHz
SCR 15:8 Serial Clock Rate = 1
CPSDVSR 7:0 even PCLK divider = 2
clk = PCLK / (CPSDVSR * [SCR+1])
clk = 30 / (2 * (1 + 1)) =
clk = 30 / 4 = 7.5 MHz
*/
}
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
inline void spi1_set_ch(int val)
{
SSPDR = val >> 12; // SSP Data Register hi 12 bits
SSPDR = val & 0x0FFF; // SSP Data Register lo 12 bits
while(SSPSR & BIT4){}; // BSY Busy. 0:idle 1:busy
}
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
inline void spi1_set(int left, int right)
{
IO0SET = BIT20; // WS P0.20 = 1:right
IO0CLR = BIT20; // WS P0.20 = 0:left
spi1_set_ch(left); // output channel
IO0SET = BIT20; // WS P0.20 = 1:right
spi1_set_ch(right); // output channel
IO0CLR = BIT20; // WS P0.20 = 0:left
}
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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