Reply by ●December 2, 20092009-12-02
Hi Steve,

I have set the SCLK to XT2/2 by setting DIVS_1 and keeping UxBR to 2 and in
this case it also worked fine.

Hi Juan Carlos,

You are right, I did not realize of that. Could also be possible that this
noise comes from a crosstalk between the probes or a bad connection to
ground because in the others is not happening.

I have tried with two boards. They have almost the same configuration.

The first one consists of one MSP430F1611 connected to the Chipcom CC2420
and two EEPROMs (the _CS and Enable of this memories are correctly
configured). The other board differs from the first one in the radio device.
The radio devices are aprox. 5mm (0.2 inches) far from the MCUs and
connected without any external pull-up/down resistor or capacitators.

Thank you,
Manuel


Beginning Microcontrollers with the MSP430

Reply by jci443 ●December 2, 20092009-12-02
Manuel,

If I understand correctly - your image, mclkdcospisclk8.png, shows the CYAN
line "lifting" 200mV
I have a few questions:
Q1
Can you explain exactly how the CS/MOSI/MISO lines interface to the MSP430?
I am interested in knowing if you are using any capacitators,pullup,or
series resistors.
(a schematic would help)
Q2
How many SPI devices are on the hardware bus?
Q3
What is the type of DC-DC converter used?
Q4
What is the %loading of the DC-DC converter?

Thank you.

Juan Carlos
On Wed, Dec 2, 2009 at 7:39 AM, Manuel Sz wrote:

> Just two more thing. I forgot to point out that:
>
> Ch4 (green) = Chip Select
> Ch3 (pink) = UCLK
> Ch1 (blue) = MOSI
> Ch2 (cyan) = MISO
>
> I also tried setting MCLK to XT2/8 synchronous to UCLK XT2/2, but I got the
> same behaviour.
>
> Regards,
> Manuel
> 2009/12/2 Manuel Sz > Hi,
> >
> > here are the pics.
> >
> > 1) This is with the MCLK sourced from the DCO at 1.2MHz. The UCLK is 1/8
> > from the XT2 = 1MHz
> > http://img694.imageshack.us/i/mclkdcospisclk82.png/
> >
> > 2) Then I changed the code to rise the CS before checking the flag in
> order
> > to compare with faster transmission. This is the result:
> > http://img109.imageshack.us/i/mclkdcospisclk8.png/
> >
> > 3) This is with the UCLK 1/4 XT2 = 2 MHZ. UCLK is faster than MCLK but
> not
> > enough to send two bytes
> > http://img140.imageshack.us/i/mclkdcospisclk4.png/
> >
> > 4) This is with the UCLK 1/2 XT2 = 4 MHZ. Here we can see the two bytes
> > transmitted:
> > http://img109.imageshack.us/i/mclkdcospisclk2.png/
> >
> > What do you think? Am I doing something wrong or could it be a hardware
> > problem?
> >
> >
> > Regards,
> > Manuel
> >
> >
> >
> > 2009/12/2 Manuel Sz
> >
> >> Hi,
> >>
> >> I have made the test. With U0BR0 = 4 or = 8 I found no problem with the
> >> communication, but when I set the U0BR0 to 2 then the SPI module sends
> the
> >> same byte twice.
> >>
> >> I am working with the MSP430F1611. I checked the MCLK clock and it is
> >> working at 1.2MHz. I've got some png files from the oscilloscope. I've
> read
> >> somewhere that I am not allowed to attach pics here. Where could I
> upload
> >> them?
> >>
> >> Here is the code:
> >>
> >> // Stop watchdog timer to prevent time out reset
> >> WDTCTL = WDTPW + WDTHOLD;
> >>
> >> DCOCTL = 0x60; // DCO set to 3
> >> BCSCTL1 = 0x03; // RSEL set to 3
> >> BCSCTL2 = 0;
> >>
> >> do {
> >> BCSCTL1 &= ~BIT7; //switch quartz to on
> >> IFG1 &= ~OFIFG; //reset status register - 0 when quartz is stable
> >> for (char i=0xff; i;i--) {__no_operation();};
> >> }while (IFG1 & OFIFG);
> >>
> >> BCSCTL2 = (BIT3 | BIT0); //enable DCO as MCLK source; Enable external
> >> quartz as SMCLK; External resistor for DCO
> >>
> >>
> >> P2SEL = BIT5; //External resistor for DCO stabilization
> >> P2DIR = ~BIT6;
> >> P2OUT = 0;
> >> P2IE = 0;
> >>
> >> P3OUT = 0;
> >> P3DIR = ~(BIT2); //All output except SPI (SOMI)
> >> P3SEL = (BIT1 | BIT2 | BIT3); // SPI
> >>
> >>
> >> //////////////////////////////////////////////////////////////
> >> /// Configure SPI hardware for proper operation
> >> ////////////////////////////////////////////////////
> >> U0CTL = SWRST;
> >> U0CTL |= CHAR | SYNC | MM;
> >> U0TCTL = 0x30 | CKPL | STC; //3 pin SPI mode, SMCLK
> >> U0BR1 = 0;
> >> U0BR0 = 8;
> >> U0MCTL = 0;
> >>
> >>
> >>
> >> //In radio transceiver P_ON state the digital pins are pulled up/down
> >> //It is important to set up the pins before initiate the device
> >> //Pag. 7 doc
> >> RF_SET_RESET_LOW();
> >> RF_SET_SLP_TR_LOW();
> >> RF_SET_CS_HIGH();
> >>
> >> RF_SLP_DIR_PORT |= RF_SLP_TR_BIT;
> >> _RF_CS_DIR_PORT |= _RF_CS_BIT;
> >>
> >> RF_SET_RESET_HIGH();
> >>
> >> for(int i = 0; i < 0xFFFF; i++);
> >>
> >> ME1 |= USPIE0;
> >> U0CTL &= ~SWRST;
> >>
> >> unsigned char addr;
> >> addr = 0x82;
> >>
> >> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
> >> register are ready
> >>
> >> RF_SET_CS_LOW();
> >> U0TXBUF = addr;
> >>
> >> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
> >> register are ready
> >> RF_SET_CS_HIGH();
> >>
> >> Regards,
> >> Manuel
> >>
> >>
> >> 2009/12/2 Manuel Sz
> >>
> >> Thanks Michael. That's exactly what I wanted to say :). I didn't find
> any
> >>> problem related to the SPI in the device errata. I will try with
> >>> different sources at the same frequency as you told, that's a good
> test.
> >>> Then I will post the results.
> >>>
> >>> Regards,
> >>> Manuel
> >>>
> >>>
> >>> 2009/12/1 Hayashi, Steve
> >>>
> >>>>
> >>>>
> >>>> Yes, I had misunderstood the original question thinking that he was
> >>>> using the MSP as an SPI slave. I tend to think of UCLK as a slave
> clock and
> >>>> ACLK & SMCLK as the master clocks.
> >>>>
> >>>>
> >>>> The only things I could think of were to check to make sure that UxBR
> >>>> was set properly. Otherwise, it sounds like it can't transfer out of
> the
> >>>> buffer fast enough.
> >>>>
> >>>> Thanks,
> >>>> -Steve
> >>>>
> >>>> From: m... [mailto:
> >>>> m... ] On Behalf Of
> Michael
> >>>> Sent: Tuesday, December 01, 2009 1:56 PM
> >>>>
> >>>> To: m...
> >>>> Subject: [msp430] Re: SPI clock faster than MCLK?
> >>>>
> >>>> Steve,
> >>>> I don't see you point. As far as I understood, for each byte the OP
> >>>> writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he
> >>>> suspects the cause is in MCLK being lower than UCLK.
> >>>> He isn't asking why there is an overrun error, he simply points out
> the
> >>>> fact that there is an overrun error which only confirms that more than
> one
> >>>> byte is being sent for each byte he writes.
> >>>>
> >>>> Manuel,
> >>>> You setup sound right to me. Have you checked the User's Guide and
> >>>> device errata?
> >>>> There is always the possibility of an 'human error', as in the
> >>>> programming of the MSP.
> >>>> After searching the errata, please post your finds. If you don't find
> >>>> anything, post the code you're using for SPI communication.
> >>>>
> >>>> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to
> >>>> UCLK.
> >>>>
> >>>> Regards,
> >>>> Michael K.
> >>>>
> >>>> --- In m... > >>>> msp430%40yahoogroups.com >, "Hayashi,
> >>>> Steve" wrote:
> >>>> >
> >>>> > To clarify what OCY is saying:
> >>>> >
> >>>> > Your code/interrupt handler operate off the MCLK. So if you supply
> the
> >>>> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or
> less),
> >>>> what do you think is going to happen?
> >>>> >
> >>>> > -Steve
> >>>> >
> >>>> > From: m... > >>>> msp430%40yahoogroups.com > [mailto:
> >>>> m... > >>>> msp430%40yahoogroups.com >] On Behalf Of
> >>>> old_cow_yellow
> >>>>
> >>>> > Sent: Tuesday, December 01, 2009 10:23 AM
> >>>> > To: m... > >>>> msp430%40yahoogroups.com >
> >>>>
> >>>> > Subject: [msp430] Re: SPI clock faster than MCLK?
> >>>> >
> >>>> >
> >>>> >
> >>>> > Have you seen (or heard about) Lucy's Chocolate Factory?
> >>>> > (One of the episodes of "I Love Lucy" around 1956.)
> >>>> >
> >>>> > --- In m... > >>>> msp430%40yahoogroups.com > > >>>> msp430%40yahoogroups.com >, Manuel Sz
> >>>> wrote:
> >>>> > >
> >>>> > > Hi everybody,
> >>>> > >
> >>>> > > I am working with the MSP430F16x to communicate with another
> device
> >>>> > > through the SPI and I think I have an error in the clock concept.
> I
> >>>> > > have look for it in the forum but I did't find the answer.
> >>>> > >
> >>>> > > I thought that the MCLK clock and the UCLK from the SPI were
> >>>> > > independent and the second one could be faster than the processor
> >>>> > > clock but it is clear that I am wrong. If I set the MCLK to derive
> >>>> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced
> from
> >>>> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI
> >>>> module
> >>>> > > sends it twice or even three times and I get an overrun error
> flag.
> >>>> I
> >>>> > > have seen this with the oscilloscope but I don't understand why it
> >>>> > > happens. Could someone explain me this?
> >>>> > >
> >>>> > > Thank you!
> >>>> > >
> >>>> >
> >>>> >
> >>>> >
> >>>> >
> >>>> >
> >>>>
> >>>>
> >>>>
> >>>>
> >>>>
> >>>
> >>>
> >>
> >
>
>
>
Reply by "Hayashi, Steve" ●December 2, 20092009-12-02
Presumably, you're setting the divider by setting UxBR. Try keeping UxBR to 2, and setting BCSCTL2 to DIVS_1 or DIVS_2.

If it doesn't work, then the problem will clearly lie with UxBR being set too low.

-Steve

-----Original Message-----
From: m... [mailto:m...] On Behalf Of Manuel Sz
Sent: Wednesday, December 02, 2009 7:39 AM
To: m...
Subject: Re: [msp430] Re: SPI clock faster than MCLK?

Just two more thing. I forgot to point out that:

Ch4 (green) = Chip Select
Ch3 (pink) = UCLK
Ch1 (blue) = MOSI
Ch2 (cyan) = MISO

I also tried setting MCLK to XT2/8 synchronous to UCLK XT2/2, but I got the
same behaviour.

Regards,
Manuel
2009/12/2 Manuel Sz

> Hi,
>
> here are the pics.
>
> 1) This is with the MCLK sourced from the DCO at 1.2MHz. The UCLK is 1/8
> from the XT2 = 1MHz
> http://img694.imageshack.us/i/mclkdcospisclk82.png/
>
> 2) Then I changed the code to rise the CS before checking the flag in order
> to compare with faster transmission. This is the result:
> http://img109.imageshack.us/i/mclkdcospisclk8.png/
>
> 3) This is with the UCLK 1/4 XT2 = 2 MHZ. UCLK is faster than MCLK but not
> enough to send two bytes
> http://img140.imageshack.us/i/mclkdcospisclk4.png/
>
> 4) This is with the UCLK 1/2 XT2 = 4 MHZ. Here we can see the two bytes
> transmitted:
> http://img109.imageshack.us/i/mclkdcospisclk2.png/
>
> What do you think? Am I doing something wrong or could it be a hardware
> problem?
> Regards,
> Manuel
>
> 2009/12/2 Manuel Sz > Hi,
>>
>> I have made the test. With U0BR0 = 4 or = 8 I found no problem with the
>> communication, but when I set the U0BR0 to 2 then the SPI module sends the
>> same byte twice.
>>
>> I am working with the MSP430F1611. I checked the MCLK clock and it is
>> working at 1.2MHz. I've got some png files from the oscilloscope. I've read
>> somewhere that I am not allowed to attach pics here. Where could I upload
>> them?
>>
>> Here is the code:
>>
>> // Stop watchdog timer to prevent time out reset
>> WDTCTL = WDTPW + WDTHOLD;
>>
>> DCOCTL = 0x60; // DCO set to 3
>> BCSCTL1 = 0x03; // RSEL set to 3
>> BCSCTL2 = 0;
>>
>> do {
>> BCSCTL1 &= ~BIT7; //switch quartz to on
>> IFG1 &= ~OFIFG; //reset status register - 0 when quartz is stable
>> for (char i=0xff; i;i--) {__no_operation();};
>> }while (IFG1 & OFIFG);
>>
>> BCSCTL2 = (BIT3 | BIT0); //enable DCO as MCLK source; Enable external
>> quartz as SMCLK; External resistor for DCO
>> P2SEL = BIT5; //External resistor for DCO stabilization
>> P2DIR = ~BIT6;
>> P2OUT = 0;
>> P2IE = 0;
>>
>> P3OUT = 0;
>> P3DIR = ~(BIT2); //All output except SPI (SOMI)
>> P3SEL = (BIT1 | BIT2 | BIT3); // SPI
>> //////////////////////////////////////////////////////////////
>> /// Configure SPI hardware for proper operation
>> ////////////////////////////////////////////////////
>> U0CTL = SWRST;
>> U0CTL |= CHAR | SYNC | MM;
>> U0TCTL = 0x30 | CKPL | STC; //3 pin SPI mode, SMCLK
>> U0BR1 = 0;
>> U0BR0 = 8;
>> U0MCTL = 0;
>>
>> //In radio transceiver P_ON state the digital pins are pulled up/down
>> //It is important to set up the pins before initiate the device
>> //Pag. 7 doc
>> RF_SET_RESET_LOW();
>> RF_SET_SLP_TR_LOW();
>> RF_SET_CS_HIGH();
>>
>> RF_SLP_DIR_PORT |= RF_SLP_TR_BIT;
>> _RF_CS_DIR_PORT |= _RF_CS_BIT;
>>
>> RF_SET_RESET_HIGH();
>>
>> for(int i = 0; i < 0xFFFF; i++);
>>
>> ME1 |= USPIE0;
>> U0CTL &= ~SWRST;
>>
>> unsigned char addr;
>> addr = 0x82;
>>
>> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
>> register are ready
>>
>> RF_SET_CS_LOW();
>> U0TXBUF = addr;
>>
>> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
>> register are ready
>> RF_SET_CS_HIGH();
>>
>> Regards,
>> Manuel
>> 2009/12/2 Manuel Sz
>>
>> Thanks Michael. That's exactly what I wanted to say :). I didn't find any
>>> problem related to the SPI in the device errata. I will try with
>>> different sources at the same frequency as you told, that's a good test.
>>> Then I will post the results.
>>>
>>> Regards,
>>> Manuel
>>>
>>>
>>> 2009/12/1 Hayashi, Steve
>>>
>>>>
>>>>
>>>> Yes, I had misunderstood the original question thinking that he was
>>>> using the MSP as an SPI slave. I tend to think of UCLK as a slave clock and
>>>> ACLK & SMCLK as the master clocks.
>>>>
>>>>
>>>> The only things I could think of were to check to make sure that UxBR
>>>> was set properly. Otherwise, it sounds like it can't transfer out of the
>>>> buffer fast enough.
>>>>
>>>> Thanks,
>>>> -Steve
>>>>
>>>> From: m... [mailto:
>>>> m... ] On Behalf Of Michael
>>>> Sent: Tuesday, December 01, 2009 1:56 PM
>>>>
>>>> To: m...
>>>> Subject: [msp430] Re: SPI clock faster than MCLK?
>>>>
>>>> Steve,
>>>> I don't see you point. As far as I understood, for each byte the OP
>>>> writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he
>>>> suspects the cause is in MCLK being lower than UCLK.
>>>> He isn't asking why there is an overrun error, he simply points out the
>>>> fact that there is an overrun error which only confirms that more than one
>>>> byte is being sent for each byte he writes.
>>>>
>>>> Manuel,
>>>> You setup sound right to me. Have you checked the User's Guide and
>>>> device errata?
>>>> There is always the possibility of an 'human error', as in the
>>>> programming of the MSP.
>>>> After searching the errata, please post your finds. If you don't find
>>>> anything, post the code you're using for SPI communication.
>>>>
>>>> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to
>>>> UCLK.
>>>>
>>>> Regards,
>>>> Michael K.
>>>>
>>>> --- In m... >>>> msp430%40yahoogroups.com >, "Hayashi,
>>>> Steve" wrote:
>>>> >
>>>> > To clarify what OCY is saying:
>>>> >
>>>> > Your code/interrupt handler operate off the MCLK. So if you supply the
>>>> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less),
>>>> what do you think is going to happen?
>>>> >
>>>> > -Steve
>>>> >
>>>> > From: m... >>>> msp430%40yahoogroups.com > [mailto:
>>>> m... >>>> msp430%40yahoogroups.com >] On Behalf Of
>>>> old_cow_yellow
>>>>
>>>> > Sent: Tuesday, December 01, 2009 10:23 AM
>>>> > To: m... >>>> msp430%40yahoogroups.com >
>>>>
>>>> > Subject: [msp430] Re: SPI clock faster than MCLK?
>>>> >
>>>> >
>>>> >
>>>> > Have you seen (or heard about) Lucy's Chocolate Factory?
>>>> > (One of the episodes of "I Love Lucy" around 1956.)
>>>> >
>>>> > --- In m... >>>> msp430%40yahoogroups.com > >>>> msp430%40yahoogroups.com >, Manuel Sz
>>>> wrote:
>>>> > >
>>>> > > Hi everybody,
>>>> > >
>>>> > > I am working with the MSP430F16x to communicate with another device
>>>> > > through the SPI and I think I have an error in the clock concept. I
>>>> > > have look for it in the forum but I did't find the answer.
>>>> > >
>>>> > > I thought that the MCLK clock and the UCLK from the SPI were
>>>> > > independent and the second one could be faster than the processor
>>>> > > clock but it is clear that I am wrong. If I set the MCLK to derive
>>>> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
>>>> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI
>>>> module
>>>> > > sends it twice or even three times and I get an overrun error flag.
>>>> I
>>>> > > have seen this with the oscilloscope but I don't understand why it
>>>> > > happens. Could someone explain me this?
>>>> > >
>>>> > > Thank you!
>>>> > >
>>>> >
>>>> >
>>>> >
>>>> >
>>>> >
>>>>
>>>>
>>>>
>>>>
>>>>
>>>
>>>
>



Reply by ●December 2, 20092009-12-02
Just two more thing. I forgot to point out that:

Ch4 (green) = Chip Select
Ch3 (pink) = UCLK
Ch1 (blue) = MOSI
Ch2 (cyan) = MISO

I also tried setting MCLK to XT2/8 synchronous to UCLK XT2/2, but I got the
same behaviour.

Regards,
Manuel
2009/12/2 Manuel Sz

> Hi,
>
> here are the pics.
>
> 1) This is with the MCLK sourced from the DCO at 1.2MHz. The UCLK is 1/8
> from the XT2 = 1MHz
> http://img694.imageshack.us/i/mclkdcospisclk82.png/
>
> 2) Then I changed the code to rise the CS before checking the flag in order
> to compare with faster transmission. This is the result:
> http://img109.imageshack.us/i/mclkdcospisclk8.png/
>
> 3) This is with the UCLK 1/4 XT2 = 2 MHZ. UCLK is faster than MCLK but not
> enough to send two bytes
> http://img140.imageshack.us/i/mclkdcospisclk4.png/
>
> 4) This is with the UCLK 1/2 XT2 = 4 MHZ. Here we can see the two bytes
> transmitted:
> http://img109.imageshack.us/i/mclkdcospisclk2.png/
>
> What do you think? Am I doing something wrong or could it be a hardware
> problem?
> Regards,
> Manuel
>
> 2009/12/2 Manuel Sz > Hi,
>>
>> I have made the test. With U0BR0 = 4 or = 8 I found no problem with the
>> communication, but when I set the U0BR0 to 2 then the SPI module sends the
>> same byte twice.
>>
>> I am working with the MSP430F1611. I checked the MCLK clock and it is
>> working at 1.2MHz. I've got some png files from the oscilloscope. I've read
>> somewhere that I am not allowed to attach pics here. Where could I upload
>> them?
>>
>> Here is the code:
>>
>> // Stop watchdog timer to prevent time out reset
>> WDTCTL = WDTPW + WDTHOLD;
>>
>> DCOCTL = 0x60; // DCO set to 3
>> BCSCTL1 = 0x03; // RSEL set to 3
>> BCSCTL2 = 0;
>>
>> do {
>> BCSCTL1 &= ~BIT7; //switch quartz to on
>> IFG1 &= ~OFIFG; //reset status register - 0 when quartz is stable
>> for (char i=0xff; i;i--) {__no_operation();};
>> }while (IFG1 & OFIFG);
>>
>> BCSCTL2 = (BIT3 | BIT0); //enable DCO as MCLK source; Enable external
>> quartz as SMCLK; External resistor for DCO
>> P2SEL = BIT5; //External resistor for DCO stabilization
>> P2DIR = ~BIT6;
>> P2OUT = 0;
>> P2IE = 0;
>>
>> P3OUT = 0;
>> P3DIR = ~(BIT2); //All output except SPI (SOMI)
>> P3SEL = (BIT1 | BIT2 | BIT3); // SPI
>> //////////////////////////////////////////////////////////////
>> /// Configure SPI hardware for proper operation
>> ////////////////////////////////////////////////////
>> U0CTL = SWRST;
>> U0CTL |= CHAR | SYNC | MM;
>> U0TCTL = 0x30 | CKPL | STC; //3 pin SPI mode, SMCLK
>> U0BR1 = 0;
>> U0BR0 = 8;
>> U0MCTL = 0;
>>
>> //In radio transceiver P_ON state the digital pins are pulled up/down
>> //It is important to set up the pins before initiate the device
>> //Pag. 7 doc
>> RF_SET_RESET_LOW();
>> RF_SET_SLP_TR_LOW();
>> RF_SET_CS_HIGH();
>>
>> RF_SLP_DIR_PORT |= RF_SLP_TR_BIT;
>> _RF_CS_DIR_PORT |= _RF_CS_BIT;
>>
>> RF_SET_RESET_HIGH();
>>
>> for(int i = 0; i < 0xFFFF; i++);
>>
>> ME1 |= USPIE0;
>> U0CTL &= ~SWRST;
>>
>> unsigned char addr;
>> addr = 0x82;
>>
>> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
>> register are ready
>>
>> RF_SET_CS_LOW();
>> U0TXBUF = addr;
>>
>> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
>> register are ready
>> RF_SET_CS_HIGH();
>>
>> Regards,
>> Manuel
>> 2009/12/2 Manuel Sz
>>
>> Thanks Michael. That's exactly what I wanted to say :). I didn't find any
>>> problem related to the SPI in the device errata. I will try with
>>> different sources at the same frequency as you told, that's a good test.
>>> Then I will post the results.
>>>
>>> Regards,
>>> Manuel
>>>
>>>
>>> 2009/12/1 Hayashi, Steve
>>>
>>>>
>>>>
>>>> Yes, I had misunderstood the original question thinking that he was
>>>> using the MSP as an SPI slave. I tend to think of UCLK as a slave clock and
>>>> ACLK & SMCLK as the master clocks.
>>>>
>>>>
>>>> The only things I could think of were to check to make sure that UxBR
>>>> was set properly. Otherwise, it sounds like it can't transfer out of the
>>>> buffer fast enough.
>>>>
>>>> Thanks,
>>>> -Steve
>>>>
>>>> From: m... [mailto:
>>>> m... ] On Behalf Of Michael
>>>> Sent: Tuesday, December 01, 2009 1:56 PM
>>>>
>>>> To: m...
>>>> Subject: [msp430] Re: SPI clock faster than MCLK?
>>>>
>>>> Steve,
>>>> I don't see you point. As far as I understood, for each byte the OP
>>>> writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he
>>>> suspects the cause is in MCLK being lower than UCLK.
>>>> He isn't asking why there is an overrun error, he simply points out the
>>>> fact that there is an overrun error which only confirms that more than one
>>>> byte is being sent for each byte he writes.
>>>>
>>>> Manuel,
>>>> You setup sound right to me. Have you checked the User's Guide and
>>>> device errata?
>>>> There is always the possibility of an 'human error', as in the
>>>> programming of the MSP.
>>>> After searching the errata, please post your finds. If you don't find
>>>> anything, post the code you're using for SPI communication.
>>>>
>>>> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to
>>>> UCLK.
>>>>
>>>> Regards,
>>>> Michael K.
>>>>
>>>> --- In m... >>>> msp430%40yahoogroups.com >, "Hayashi,
>>>> Steve" wrote:
>>>> >
>>>> > To clarify what OCY is saying:
>>>> >
>>>> > Your code/interrupt handler operate off the MCLK. So if you supply the
>>>> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less),
>>>> what do you think is going to happen?
>>>> >
>>>> > -Steve
>>>> >
>>>> > From: m... >>>> msp430%40yahoogroups.com > [mailto:
>>>> m... >>>> msp430%40yahoogroups.com >] On Behalf Of
>>>> old_cow_yellow
>>>>
>>>> > Sent: Tuesday, December 01, 2009 10:23 AM
>>>> > To: m... >>>> msp430%40yahoogroups.com >
>>>>
>>>> > Subject: [msp430] Re: SPI clock faster than MCLK?
>>>> >
>>>> >
>>>> >
>>>> > Have you seen (or heard about) Lucy's Chocolate Factory?
>>>> > (One of the episodes of "I Love Lucy" around 1956.)
>>>> >
>>>> > --- In m... >>>> msp430%40yahoogroups.com > >>>> msp430%40yahoogroups.com >, Manuel Sz
>>>> wrote:
>>>> > >
>>>> > > Hi everybody,
>>>> > >
>>>> > > I am working with the MSP430F16x to communicate with another device
>>>> > > through the SPI and I think I have an error in the clock concept. I
>>>> > > have look for it in the forum but I did't find the answer.
>>>> > >
>>>> > > I thought that the MCLK clock and the UCLK from the SPI were
>>>> > > independent and the second one could be faster than the processor
>>>> > > clock but it is clear that I am wrong. If I set the MCLK to derive
>>>> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
>>>> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI
>>>> module
>>>> > > sends it twice or even three times and I get an overrun error flag.
>>>> I
>>>> > > have seen this with the oscilloscope but I don't understand why it
>>>> > > happens. Could someone explain me this?
>>>> > >
>>>> > > Thank you!
>>>> > >
>>>> >
>>>> >
>>>> >
>>>> >
>>>> >
>>>>
>>>>
>>>>
>>>>
>>>>
>>>
>>>
>



Reply by ●December 2, 20092009-12-02
Hi,

here are the pics.

1) This is with the MCLK sourced from the DCO at 1.2MHz. The UCLK is 1/8
from the XT2 = 1MHz
http://img694.imageshack.us/i/mclkdcospisclk82.png/

2) Then I changed the code to rise the CS before checking the flag in order
to compare with faster transmission. This is the result:
http://img109.imageshack.us/i/mclkdcospisclk8.png/

3) This is with the UCLK 1/4 XT2 = 2 MHZ. UCLK is faster than MCLK but not
enough to send two bytes
http://img140.imageshack.us/i/mclkdcospisclk4.png/

4) This is with the UCLK 1/2 XT2 = 4 MHZ. Here we can see the two bytes
transmitted:
http://img109.imageshack.us/i/mclkdcospisclk2.png/

What do you think? Am I doing something wrong or could it be a hardware
problem?

Regards,
Manuel

2009/12/2 Manuel Sz

> Hi,
>
> I have made the test. With U0BR0 = 4 or = 8 I found no problem with the
> communication, but when I set the U0BR0 to 2 then the SPI module sends the
> same byte twice.
>
> I am working with the MSP430F1611. I checked the MCLK clock and it is
> working at 1.2MHz. I've got some png files from the oscilloscope. I've read
> somewhere that I am not allowed to attach pics here. Where could I upload
> them?
>
> Here is the code:
>
> // Stop watchdog timer to prevent time out reset
> WDTCTL = WDTPW + WDTHOLD;
>
> DCOCTL = 0x60; // DCO set to 3
> BCSCTL1 = 0x03; // RSEL set to 3
> BCSCTL2 = 0;
>
> do {
> BCSCTL1 &= ~BIT7; //switch quartz to on
> IFG1 &= ~OFIFG; //reset status register - 0 when quartz is stable
> for (char i=0xff; i;i--) {__no_operation();};
> }while (IFG1 & OFIFG);
>
> BCSCTL2 = (BIT3 | BIT0); //enable DCO as MCLK source; Enable external
> quartz as SMCLK; External resistor for DCO
> P2SEL = BIT5; //External resistor for DCO stabilization
> P2DIR = ~BIT6;
> P2OUT = 0;
> P2IE = 0;
>
> P3OUT = 0;
> P3DIR = ~(BIT2); //All output except SPI (SOMI)
> P3SEL = (BIT1 | BIT2 | BIT3); // SPI
> //////////////////////////////////////////////////////////////
> /// Configure SPI hardware for proper operation
> ////////////////////////////////////////////////////
> U0CTL = SWRST;
> U0CTL |= CHAR | SYNC | MM;
> U0TCTL = 0x30 | CKPL | STC; //3 pin SPI mode, SMCLK
> U0BR1 = 0;
> U0BR0 = 8;
> U0MCTL = 0;
>
> //In radio transceiver P_ON state the digital pins are pulled up/down
> //It is important to set up the pins before initiate the device
> //Pag. 7 doc
> RF_SET_RESET_LOW();
> RF_SET_SLP_TR_LOW();
> RF_SET_CS_HIGH();
>
> RF_SLP_DIR_PORT |= RF_SLP_TR_BIT;
> _RF_CS_DIR_PORT |= _RF_CS_BIT;
>
> RF_SET_RESET_HIGH();
>
> for(int i = 0; i < 0xFFFF; i++);
>
> ME1 |= USPIE0;
> U0CTL &= ~SWRST;
>
> unsigned char addr;
> addr = 0x82;
>
> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
> register are ready
>
> RF_SET_CS_LOW();
> U0TXBUF = addr;
>
> while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
> register are ready
> RF_SET_CS_HIGH();
>
> Regards,
> Manuel
> 2009/12/2 Manuel Sz Thanks Michael. That's exactly what I wanted to say :). I didn't find any
>> problem related to the SPI in the device errata. I will try with
>> different sources at the same frequency as you told, that's a good test.
>> Then I will post the results.
>>
>> Regards,
>> Manuel
>> 2009/12/1 Hayashi, Steve
>>
>>>
>>>
>>> Yes, I had misunderstood the original question thinking that he was using
>>> the MSP as an SPI slave. I tend to think of UCLK as a slave clock and ACLK &
>>> SMCLK as the master clocks.
>>>
>>>
>>> The only things I could think of were to check to make sure that UxBR was
>>> set properly. Otherwise, it sounds like it can't transfer out of the buffer
>>> fast enough.
>>>
>>> Thanks,
>>> -Steve
>>>
>>> From: m... [mailto:
>>> m... ] On Behalf Of Michael
>>> Sent: Tuesday, December 01, 2009 1:56 PM
>>>
>>> To: m...
>>> Subject: [msp430] Re: SPI clock faster than MCLK?
>>>
>>> Steve,
>>> I don't see you point. As far as I understood, for each byte the OP
>>> writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he
>>> suspects the cause is in MCLK being lower than UCLK.
>>> He isn't asking why there is an overrun error, he simply points out the
>>> fact that there is an overrun error which only confirms that more than one
>>> byte is being sent for each byte he writes.
>>>
>>> Manuel,
>>> You setup sound right to me. Have you checked the User's Guide and device
>>> errata?
>>> There is always the possibility of an 'human error', as in the
>>> programming of the MSP.
>>> After searching the errata, please post your finds. If you don't find
>>> anything, post the code you're using for SPI communication.
>>>
>>> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to
>>> UCLK.
>>>
>>> Regards,
>>> Michael K.
>>>
>>> --- In m... >>> msp430%40yahoogroups.com >, "Hayashi, Steve"
>>> wrote:
>>> >
>>> > To clarify what OCY is saying:
>>> >
>>> > Your code/interrupt handler operate off the MCLK. So if you supply the
>>> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less),
>>> what do you think is going to happen?
>>> >
>>> > -Steve
>>> >
>>> > From: m... >>> msp430%40yahoogroups.com > [mailto:
>>> m... >>> msp430%40yahoogroups.com >] On Behalf Of
>>> old_cow_yellow
>>>
>>> > Sent: Tuesday, December 01, 2009 10:23 AM
>>> > To: m... >>> msp430%40yahoogroups.com >
>>>
>>> > Subject: [msp430] Re: SPI clock faster than MCLK?
>>> >
>>> >
>>> >
>>> > Have you seen (or heard about) Lucy's Chocolate Factory?
>>> > (One of the episodes of "I Love Lucy" around 1956.)
>>> >
>>> > --- In m... >>> msp430%40yahoogroups.com > >>> msp430%40yahoogroups.com >, Manuel Sz
>>> wrote:
>>> > >
>>> > > Hi everybody,
>>> > >
>>> > > I am working with the MSP430F16x to communicate with another device
>>> > > through the SPI and I think I have an error in the clock concept. I
>>> > > have look for it in the forum but I did't find the answer.
>>> > >
>>> > > I thought that the MCLK clock and the UCLK from the SPI were
>>> > > independent and the second one could be faster than the processor
>>> > > clock but it is clear that I am wrong. If I set the MCLK to derive
>>> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
>>> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
>>> > > sends it twice or even three times and I get an overrun error flag. I
>>> > > have seen this with the oscilloscope but I don't understand why it
>>> > > happens. Could someone explain me this?
>>> > >
>>> > > Thank you!
>>> > >
>>> >
>>> >
>>> >
>>> >
>>> >
>>>
>>>
>>>
>>>
>>



Reply by ●December 2, 20092009-12-02
Hi,

I have made the test. With U0BR0 = 4 or = 8 I found no problem with the
communication, but when I set the U0BR0 to 2 then the SPI module sends the
same byte twice.

I am working with the MSP430F1611. I checked the MCLK clock and it is
working at 1.2MHz. I've got some png files from the oscilloscope. I've read
somewhere that I am not allowed to attach pics here. Where could I upload
them?

Here is the code:

// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;

DCOCTL = 0x60; // DCO set to 3
BCSCTL1 = 0x03; // RSEL set to 3
BCSCTL2 = 0;

do {
BCSCTL1 &= ~BIT7; //switch quartz to on
IFG1 &= ~OFIFG; //reset status register - 0 when quartz is stable
for (char i=0xff; i;i--) {__no_operation();};
}while (IFG1 & OFIFG);

BCSCTL2 = (BIT3 | BIT0); //enable DCO as MCLK source; Enable external
quartz as SMCLK; External resistor for DCO
P2SEL = BIT5; //External resistor for DCO stabilization
P2DIR = ~BIT6;
P2OUT = 0;
P2IE = 0;

P3OUT = 0;
P3DIR = ~(BIT2); //All output except SPI (SOMI)
P3SEL = (BIT1 | BIT2 | BIT3); // SPI
//////////////////////////////////////////////////////////////
/// Configure SPI hardware for proper operation
////////////////////////////////////////////////////
U0CTL = SWRST;
U0CTL |= CHAR | SYNC | MM;
U0TCTL = 0x30 | CKPL | STC; //3 pin SPI mode, SMCLK
U0BR1 = 0;
U0BR0 = 8;
U0MCTL = 0;

//In radio transceiver P_ON state the digital pins are pulled up/down
//It is important to set up the pins before initiate the device
//Pag. 7 doc
RF_SET_RESET_LOW();
RF_SET_SLP_TR_LOW();
RF_SET_CS_HIGH();

RF_SLP_DIR_PORT |= RF_SLP_TR_BIT;
_RF_CS_DIR_PORT |= _RF_CS_BIT;

RF_SET_RESET_HIGH();

for(int i = 0; i < 0xFFFF; i++);

ME1 |= USPIE0;
U0CTL &= ~SWRST;

unsigned char addr;
addr = 0x82;

while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
register are ready

RF_SET_CS_LOW();
U0TXBUF = addr;

while( (U0TCTL & TXEPT) != TXEPT); //waits until buffer and shift
register are ready
RF_SET_CS_HIGH();

Regards,
Manuel
2009/12/2 Manuel Sz

> Thanks Michael. That's exactly what I wanted to say :). I didn't find any
> problem related to the SPI in the device errata. I will try with different
> sources at the same frequency as you told, that's a good test. Then I will
> post the results.
>
> Regards,
> Manuel
> 2009/12/1 Hayashi, Steve > Yes, I had misunderstood the original question thinking that he was using
>> the MSP as an SPI slave. I tend to think of UCLK as a slave clock and ACLK &
>> SMCLK as the master clocks.
>> The only things I could think of were to check to make sure that UxBR was
>> set properly. Otherwise, it sounds like it can't transfer out of the buffer
>> fast enough.
>>
>> Thanks,
>> -Steve
>>
>> From: m... [mailto:
>> m... ] On Behalf Of Michael
>> Sent: Tuesday, December 01, 2009 1:56 PM
>>
>> To: m...
>> Subject: [msp430] Re: SPI clock faster than MCLK?
>>
>> Steve,
>> I don't see you point. As far as I understood, for each byte the OP writes
>> to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he suspects the
>> cause is in MCLK being lower than UCLK.
>> He isn't asking why there is an overrun error, he simply points out the
>> fact that there is an overrun error which only confirms that more than one
>> byte is being sent for each byte he writes.
>>
>> Manuel,
>> You setup sound right to me. Have you checked the User's Guide and device
>> errata?
>> There is always the possibility of an 'human error', as in the programming
>> of the MSP.
>> After searching the errata, please post your finds. If you don't find
>> anything, post the code you're using for SPI communication.
>>
>> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to
>> UCLK.
>>
>> Regards,
>> Michael K.
>>
>> --- In m... >> msp430%40yahoogroups.com >, "Hayashi, Steve"
>> wrote:
>> >
>> > To clarify what OCY is saying:
>> >
>> > Your code/interrupt handler operate off the MCLK. So if you supply the
>> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less),
>> what do you think is going to happen?
>> >
>> > -Steve
>> >
>> > From: m... >> msp430%40yahoogroups.com > [mailto:
>> m... >> msp430%40yahoogroups.com >] On Behalf Of
>> old_cow_yellow
>>
>> > Sent: Tuesday, December 01, 2009 10:23 AM
>> > To: m... >> msp430%40yahoogroups.com > > Subject: [msp430] Re: SPI clock faster than MCLK?
>> >
>> >
>> >
>> > Have you seen (or heard about) Lucy's Chocolate Factory?
>> > (One of the episodes of "I Love Lucy" around 1956.)
>> >
>> > --- In m... >> msp430%40yahoogroups.com > >> msp430%40yahoogroups.com >, Manuel Sz
>> wrote:
>> > >
>> > > Hi everybody,
>> > >
>> > > I am working with the MSP430F16x to communicate with another device
>> > > through the SPI and I think I have an error in the clock concept. I
>> > > have look for it in the forum but I did't find the answer.
>> > >
>> > > I thought that the MCLK clock and the UCLK from the SPI were
>> > > independent and the second one could be faster than the processor
>> > > clock but it is clear that I am wrong. If I set the MCLK to derive
>> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
>> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
>> > > sends it twice or even three times and I get an overrun error flag. I
>> > > have seen this with the oscilloscope but I don't understand why it
>> > > happens. Could someone explain me this?
>> > >
>> > > Thank you!
>> > >
>> >
>> >
>> >
>> >
>> >
>>
>>
>>
>>
>>


Reply by ●December 2, 20092009-12-02
Thanks Michael. That's exactly what I wanted to say :). I didn't find any
problem related to the SPI in the device errata. I will try with different
sources at the same frequency as you told, that's a good test. Then I will
post the results.

Regards,
Manuel
2009/12/1 Hayashi, Steve

> Yes, I had misunderstood the original question thinking that he was using
> the MSP as an SPI slave. I tend to think of UCLK as a slave clock and ACLK &
> SMCLK as the master clocks.
>
> The only things I could think of were to check to make sure that UxBR was
> set properly. Otherwise, it sounds like it can't transfer out of the buffer
> fast enough.
>
> Thanks,
> -Steve
>
> From: m... [mailto:
> m... ] On Behalf Of Michael
> Sent: Tuesday, December 01, 2009 1:56 PM
>
> To: m...
> Subject: [msp430] Re: SPI clock faster than MCLK?
>
> Steve,
> I don't see you point. As far as I understood, for each byte the OP writes
> to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he suspects the
> cause is in MCLK being lower than UCLK.
> He isn't asking why there is an overrun error, he simply points out the
> fact that there is an overrun error which only confirms that more than one
> byte is being sent for each byte he writes.
>
> Manuel,
> You setup sound right to me. Have you checked the User's Guide and device
> errata?
> There is always the possibility of an 'human error', as in the programming
> of the MSP.
> After searching the errata, please post your finds. If you don't find
> anything, post the code you're using for SPI communication.
>
> Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to UCLK.
>
> Regards,
> Michael K.
>
> --- In m... > msp430%40yahoogroups.com >, "Hayashi, Steve"
> wrote:
> >
> > To clarify what OCY is saying:
> >
> > Your code/interrupt handler operate off the MCLK. So if you supply the
> cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less),
> what do you think is going to happen?
> >
> > -Steve
> >
> > From: m... > msp430%40yahoogroups.com > [mailto:
> m... > msp430%40yahoogroups.com >] On Behalf Of
> old_cow_yellow
>
> > Sent: Tuesday, December 01, 2009 10:23 AM
> > To: m... > msp430%40yahoogroups.com > > Subject: [msp430] Re: SPI clock faster than MCLK?
> >
> >
> >
> > Have you seen (or heard about) Lucy's Chocolate Factory?
> > (One of the episodes of "I Love Lucy" around 1956.)
> >
> > --- In m... > msp430%40yahoogroups.com > > msp430%40yahoogroups.com >, Manuel Sz
> wrote:
> > >
> > > Hi everybody,
> > >
> > > I am working with the MSP430F16x to communicate with another device
> > > through the SPI and I think I have an error in the clock concept. I
> > > have look for it in the forum but I did't find the answer.
> > >
> > > I thought that the MCLK clock and the UCLK from the SPI were
> > > independent and the second one could be faster than the processor
> > > clock but it is clear that I am wrong. If I set the MCLK to derive
> > > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
> > > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
> > > sends it twice or even three times and I get an overrun error flag. I
> > > have seen this with the oscilloscope but I don't understand why it
> > > happens. Could someone explain me this?
> > >
> > > Thank you!
> > >
> >
> >
> >
> >
> >
>
>
>


Reply by "Hayashi, Steve" ●December 1, 20092009-12-01
Yes, I had misunderstood the original question thinking that he was using the MSP as an SPI slave. I tend to think of UCLK as a slave clock and ACLK & SMCLK as the master clocks.

The only things I could think of were to check to make sure that UxBR was set properly. Otherwise, it sounds like it can't transfer out of the buffer fast enough.

Thanks,
-Steve

From: m... [mailto:m...] On Behalf Of Michael
Sent: Tuesday, December 01, 2009 1:56 PM
To: m...
Subject: [msp430] Re: SPI clock faster than MCLK?

Steve,
I don't see you point. As far as I understood, for each byte the OP writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he suspects the cause is in MCLK being lower than UCLK.
He isn't asking why there is an overrun error, he simply points out the fact that there is an overrun error which only confirms that more than one byte is being sent for each byte he writes.

Manuel,
You setup sound right to me. Have you checked the User's Guide and device errata?
There is always the possibility of an 'human error', as in the programming of the MSP.
After searching the errata, please post your finds. If you don't find anything, post the code you're using for SPI communication.

Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to UCLK.

Regards,
Michael K.

--- In m..., "Hayashi, Steve" wrote:
>
> To clarify what OCY is saying:
>
> Your code/interrupt handler operate off the MCLK. So if you supply the cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less), what do you think is going to happen?
>
> -Steve
>
> From: m... [mailto:msp4...] On Behalf Of old_cow_yellow
> Sent: Tuesday, December 01, 2009 10:23 AM
> To: m...
> Subject: [msp430] Re: SPI clock faster than MCLK?
>
> Have you seen (or heard about) Lucy's Chocolate Factory?
> (One of the episodes of "I Love Lucy" around 1956.)
>
> --- In m..., Manuel Sz wrote:
> >
> > Hi everybody,
> >
> > I am working with the MSP430F16x to communicate with another device
> > through the SPI and I think I have an error in the clock concept. I
> > have look for it in the forum but I did't find the answer.
> >
> > I thought that the MCLK clock and the UCLK from the SPI were
> > independent and the second one could be faster than the processor
> > clock but it is clear that I am wrong. If I set the MCLK to derive
> > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
> > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
> > sends it twice or even three times and I get an overrun error flag. I
> > have seen this with the oscilloscope but I don't understand why it
> > happens. Could someone explain me this?
> >
> > Thank you!
> >
>



Reply by Michael ●December 1, 20092009-12-01
Steve,
I don't see you point. As far as I understood, for each byte the OP writes to the TXBUF he sees 2 to 3 bytes sent on the SPI bus, and he suspects the cause is in MCLK being lower than UCLK.
He isn't asking why there is an overrun error, he simply points out the fact that there is an overrun error which only confirms that more than one byte is being sent for each byte he writes.

Manuel,
You setup sound right to me. Have you checked the User's Guide and device errata?
There is always the possibility of an 'human error', as in the programming of the MSP.
After searching the errata, please post your finds. If you don't find anything, post the code you're using for SPI communication.

Also try setting MCLK to XT2/8, which is also 1MHz but synchronous to UCLK.

Regards,
Michael K.

--- In m..., "Hayashi, Steve" wrote:
>
> To clarify what OCY is saying:
>
> Your code/interrupt handler operate off the MCLK. So if you supply the cpu with data at 4MHz, but the CPU can only process it at 1MHz (or less), what do you think is going to happen?
>
> -Steve
>
> From: m... [mailto:m...] On Behalf Of old_cow_yellow
> Sent: Tuesday, December 01, 2009 10:23 AM
> To: m...
> Subject: [msp430] Re: SPI clock faster than MCLK?
>
>
>
> Have you seen (or heard about) Lucy's Chocolate Factory?
> (One of the episodes of "I Love Lucy" around 1956.)
>
> --- In m..., Manuel Sz wrote:
> >
> > Hi everybody,
> >
> > I am working with the MSP430F16x to communicate with another device
> > through the SPI and I think I have an error in the clock concept. I
> > have look for it in the forum but I did't find the answer.
> >
> > I thought that the MCLK clock and the UCLK from the SPI were
> > independent and the second one could be faster than the processor
> > clock but it is clear that I am wrong. If I set the MCLK to derive
> > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
> > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
> > sends it twice or even three times and I get an overrun error flag. I
> > have seen this with the oscilloscope but I don't understand why it
> > happens. Could someone explain me this?
> >
> > Thank you!
> >
>
>
>
>
>

Reply by "e.tury" ●December 1, 20092009-12-01
I'm pretty sure it was a pie factory.

--- In m..., "old_cow_yellow" wrote:
>
> Have you seen (or heard about) Lucy's Chocolate Factory?
> (One of the episodes of "I Love Lucy" around 1956.)
>
> --- In m..., Manuel Sz wrote:
> >
> > Hi everybody,
> >
> > I am working with the MSP430F16x to communicate with another device
> > through the SPI and I think I have an error in the clock concept. I
> > have look for it in the forum but I did't find the answer.
> >
> > I thought that the MCLK clock and the UCLK from the SPI were
> > independent and the second one could be faster than the processor
> > clock but it is clear that I am wrong. If I set the MCLK to derive
> > from the DCO (~1MHz) and the UCLK is half of the SMCLK (sourced from
> > the 8MHz XT2), for each byte I write in the Tx buffer, the SPI module
> > sends it twice or even three times and I get an overrun error flag. I
> > have seen this with the oscilloscope but I don't understand why it
> > happens. Could someone explain me this?
> >
> > Thank you!
>